®
®
ADS-325A
for VRB, which give an analog input range of +2V to +4V.
The reference voltages must be within the following
limitations:
+AVS – 0.4V > = VRT > VRB >= +1.8V, and
VRT – VRB > =1.8V
Stability of the reference will directly affect the accuracy of
the A/D conversion. In this sense, the reference sources
must be capable of driving more than 10mA. Also, the VRT
and VRB pins should be bypassed to analog ground with
0.1µF ceramic capacitors placed as close to the pins as
possible.
5.
Analog Input:
ADS-325A has a broad input bandwidth of
70MHz (@–1dB) with only 9pF of input capacitance at its
analog input. The analog input should be driven by a high
speed buffer amplifier with sufficient current drive.
6.
Digital Inputs:
All digital input pins including A/D clock input
are CMOS compatible. Each of these pins has an internal
overvoltage protection circuit with diodes as shown in Figure
2 (Equivalent circuit diagrams).
7.
Control Logic Inputs:
ADS-325A has several control logic
input pins. Functions of these pins are described in the
following:
TEST MODE (pin 19), MINV (pin 21), LINV (pin 20)
These three pins select the output data format. With a
combination of these input states the output data takes any
form of binary, complementary binary, 2's compliment, or
certain test pattern. Refer to Table 1 (Output coding) and
Table 2 (Truth table).
CE (Chip Enable, pin 24)
For normal operation the input to this pin should be logic
low. Input high applied to the pin puts the unit into standby
mode. In standby mode the unit dissipates only a few milli-
watts or less.
OE (Output Enable, pin 23)
Input logic low applied to this pin enables the three-state
output bits (Bit 1 to Bit 10). Input high disables the outputs.
RESET (pin 15)
This pin can be used to re-initiate start-up calibration.
Normally connect this pin to logic high. See Calibration
Function for more details.
CAL (Calibration Input, pin 41)
This pin is the input for an external calibration pulse. See
Calibration Function for more details.
SEL (Select, pin 17)
Applying logic high to this pin allows use of the internal auto
calibration function and blocks out the external pulse from
the CAL input. Inputting logic low to the pin disables the
internal cal function and allows usage of the external cal
pulses.
8.
Test IN/OUT pins:
Test signal input/output pins are used in
the production process. The test signal output pins (pin 13,
38) should normally be left open. Tie the test signal input pin
42 to +AV
S
and the pins 14 and 37 to +AV
S
or AGND.
9.
Three-state output buffer:
A/D output buffer (BIT 1 to
BIT 10) is a three-state register controlled by the OE pin.
The output logic high level is dependent on +DV
S
.
+DV
S
+AV
S
39
V
IN
OUTPUT
BIT
AGND
DGND
Analog Signal Input
+AV
S
Digital Data Outputs
+AV
S
29
30 V
RT
RESET 15
SELECT 17
TEST MODE 19
LINV 20
MINV 21
CLOCK 22
OUTPUT ENABLE (OE) 23
CHIP ENABLE (CE) 24
CAL. PULSE IN (CAL) 41
AGND
AGND
34
35
+AV
S
AGND
V
RB
SEL, CLK, CAL, RESET, OE, CE, Test Mode,
LINV and MINV Inputs
Figure 2. Equivelant Circuits
Reference Input
3
MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
