ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Reset
Feedthrough
Glitch
Pixel Data
N+2
CCD
OUTPUT
Reference N
Pixel
Data N
Ref. N+1
Pixel Data
N+1
Ref. N+2
Ref. N+3
Pixel Data
N+3
Ref. N+4
REFERENCE
HOLD
(Pin 26)
Pixel Data
Settling Time
Reference Hold
t
3
t
2
Reference
Acquisition
Time
CDS
OUTPUT
Full Scale Step
(Vsat)
N
t
1
N+1
t
4
N+2
N+3
START CONVERT
(Pin 25)
90ns typ.
DATA VALID
(Pin 27)
Data Invalid
DATA
10ns min.
30ns max.
N-1 Data Valid
Data Invalid
Data Invalid
Data Invalid
* 20ns min.
N Data Valid
N+1 Data Valid
N+2 Data Valid
* Output Data guaranteed to be valid a minimum of 20ns after falling edge of DATA VALID (pin 27).
++ CDS Output captured by S/H at rising edge of Start Convert (pin 25).
Figure 8. ADCDS-1603 Timing Diagram
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
Figure 9. ADCDS-1603 Differential Nonlinearity, LSBs
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Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADCDS-1603.E06 Page 8 of 11
MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
