ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Fine Gain Adjustment
For fine gain adjustment model, contact the factory.
Output Coding
The ADCDS-1603's output coding is Straight Binary as indicated in
Table 1. The table shows the relationship between the output data
coding and the difference between the reference signal voltage and
its corresponding pixel data signal voltage.
Table 1. Output Coding
Reference – Pixel Data
(V)
>+2.048
2.048
1.536
1.024
0.512
0.256
0.00003125
0
<0
Scale
>Full Scale
Full Scale -1LSB
3/4FS
1/2FS
1/4FS
1/8FS
1LSB
0
<0
Digital Output
1111 1111 1111 1111
1111 1111 1111 1110
11 0000 0000 0000
10 0000 0000 0000
01 0000 0000 0000
00 1000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
0000 0000 0000 0000
Optimal Performance
Disturbances to the system while the A/D is undergoing a conversion
can result in degradation of performance. It is therefore recommended
that both digital and analog signals (including the Reference/Pixel data
inputs to the ADCDS) not be allowed to switch during a time window of
150ns to 300ns following the rising edge of the Start Convert command
when operating in the 0°C to 70°C temperature range, and from 140ns
to 320ns for the extended temperature range. See timing Figure 7
"A/D Critical Conversion Window."
The max conversion rate of 2.3MHz for the ADCDS-1603 is dictated by
the settling time of the input circuitry and the conversion time require-
ment of the A/D converter. Switching the analog input from Reference
to pixel data 300ns after the rising edge of Start Convert allows a suf-
ficient amount of settling time (approx. 130ns) for the pixel data input
signal to settle to the 16 bit accuracy. In the unique application where
the Reference to Pixel data signal is presented to the ADCDS-1603 prior
to the 120ns to 300ns restriction it may be possible to increase the
ADCDS-1603 conversion rate up to 3MHz.
Note:
At initial power-up, the first 186 conversions should be ignored.
Resultant signal from internal CDS (Input to A/D). Assumes Input Amplifier gain set properly.
See "Modes of Operation" section.
The pixel data portion of the differential signal must be more negative than its associated
reference level and V
OUT
should not exceed +2.048V DC.
+5VD
4.7μF
–5VA
4.7μF
+5VA
4.7μF
0.1μF
34
6
4.7μF
0.1μF
External Series
Resistor
+2.048V REFERENCE OUT
0.1μF
38
0.1μF
36
23 BIT 1 (MSB)
22 BIT 2
21 BIT 3
20 BIT 4
19 BIT 5
18 BIT 6
17 BIT 7
16 BIT 8
15 BIT 9
14 BIT 10
13 BIT 11
12 BIT 12
11 BIT 13
10 BIT 14
9
8
BIT 15
BIT 16 (LSB)
ADCDS-1603
2
3
OFFSET ADJUST
DIRECT INPUT
INVERTING INPUT
5
NON-INVERTING INPUT
30
A0
31
A1
+5V
20K
–5V
See
Figures
2a–2f
4
0.1μF
0.1μF
25
START CONVERT
26
REF. HOLD
7, 35, 37
ANALOG GROUND
27
DATA VALID
32, 33 DIGITAL GROUND
Figure 6. ADCDS-1603 Connection Diagram
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADCDS-1603.E06 Page 5 of 11
MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
