ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Non-Inverting Mode
The non-inverting mode of the ADCDS-1603 allows the designer to either
attenuate or add non-inverting gain to the pixel data input signal. This
configuration also allows bypassing the ADCDS-1603's internal coupling
capacitor, allowing the user to provide an external capacitor of appropriate
value.
Figure 2c. describes the typical configuration for applications using pixel
data input signals with amplitudes greater than 0.342Vp-p and less than
2.048Vp-p. Using a single external series resistor, the coarse gain of the
ADCDS-1603 can be set. The coarse gain of the circuit can be determined
from the following equation:
V
OUT
= 2.048Vp-p = V
IN
*(1+(499/(100+Rext))),
with all internal resistors having a 0.1% tolerance.
Figure 2d. describes the typical configuration for applications using a
pixel data input signal whose amplitude is greater than 2.048Vp-p. Using
a single external series resistor (Rext 1) in conjunction with the internal
5K (1%) resistor to ground, an attenuation of the input signal can be
achieved. The coarse gain of this circuit can be determined from the
following equation:
V
OUT
= 2.048Vp-p = [V
IN
*(5000/(Rext1+5000))]*
[1+(499/(100+Rext2))],
with all internal resistors having a 0.1% tolerance.
Inverting Mode
The inverting mode of operation can be used in applications where the
analog input to the ADCDS-1603 has a pixel data input signal whose
amplitude is more positive than its associated reference level. The
ADCDS-1603's correlated double sampler (i.e. input amplifier's V
OUT
)
requires that the pixel data signal's amplitude be more negative than its
reference level at all times (see timing diagram for details). Using the
ADCDS-1603 in the inverting mode allows the designer to perform an
additional signal inversion to correct for any analog "front end" pre-
processing that may have occurred prior to the ADCDS-1603.
Figure 2e. describes the typical configuration for applications using a pixel
data input signal with a maximum amplitude of 0.342Vp-p. The coarse
gain of this circuit can be determined from the following equation:
V
OUT
= 2.048Vp-p = –V
IN
*(499/100),
with all internal resistors having a 0.1% tolerance.
Figure 2f. describes the typical configuration used in applications
needing to invert pixel data input signals whose amplitude is greater
than 0.342Vp-p. Using a single external series resistor, the initial gain
of the ADCDS-1603 can be set. The coarse gain of this circuit can be
determined from the following equation:
V
OUT
= 2.048Vp-p = –V
IN
*(499/100+Rext),
with all internal resistors having a 0.1% tolerance.
Offset Adjustment
Manual offset adjustment for the ADCDS-1603 can be accomplished
using the adjustment circuit shown in Figure 3. A software controlled
D/A converter can be substituted for the 20KΩ potentiometer. The offset
adjustment feature allows the user to adjust the Offset/Dark Current level
of the ADCDS-1603 until the output bits are 00 0000 0000 0000 and the
LSB flickers between 0 and 1. The ADCDS-1603's offset adjustment is
dependent on the value of the external series resistor used in the offset
adjust circuit (Figure 3) and the gain of the input-amplifier.
It should be noted that with increasing amounts of offset adjustment
(smaller values of external series resistors), the ADCDS-1603 becomes
more susceptible to power supply noise or voltage variations seen at the
wiper of the offset potentiometer.
Rext2
4
100
499
–V
IN
Rext
4
100
499
3
NO CONNECT
Rext1
V
IN
5
0.01μF
V
OUT
= 2.048Vp-p
NO CONNECT
3
5
0.01μf
V
OUT
= 2.048Vp-p
5k
22pf
5k
22pf
Figure 2d. Non-inverting Mode
Figure 2f. Inverting Mode
–V
IN
4
100
499
+5V
External
Series
Resistor
ADCDS-1603
NO CONNECT
3
5
0.01μf
V
OUT
= 2.048Vp-p
20k
Offset
Adjust
2
5k
22pf
–5V
Figure 2e. Inverting Mode
Figure 3. Offset Adjustment Circuit
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADCDS-1603.E06 Page 4 of 11
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