MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR
Capacitors
to the FB pin consisting of R4 and C4.The ramp
voltage, VRAMP, and the resistor divider influence
the output voltage as shown in Figure 11.
Calculate VRAMP as shown in equation 7. Select
R2 to balance between high quiescent current
loss and FB noise sensitivity. Choose R2 within
5kΩ to 50kΩ, using a larger R2 when VOUT is low,
and a smaller R2 when VOUT is high. Determine
the value of R1 as follows:
For applications that electrolytic capacitor or POS
capacitor with a large ESR is set as output
capacitors. The feedback resistors—R1 and R2
as shown in Figure 10—set the output voltage.
SW
L
VOUT
FB
R2
ESR
POSCAP
R1
R2
(16)
R1
VFB(AVG)
R2
VOUT VFB(AVG) R4 R9
Where VFB(AVG) is the average FB voltage. VFB(AVG)
varies with the VIN, VOUT, and load condition,
where the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG); improving the load or line regulation
involves a lower VRAMP that meets equation 9.
Figure10—Simplified POSCAP Circuit
First, choose a value for R2 that balances
between high quiescent current loss (low R2) and
high noise sensitivity on FB (high R2). A typical
value falls within 5kΩ to 50kΩ, using a
comparatively larger R2 when VOUT is low, and a
smaller R2 when VOUT is high. Then calculate R1
as follows, which considers the output ripple:
For PWM operation, estimate VFB(AVG) from
equation 17.
1
2
R1//R2
(17)
VFB(AVG) VREF
VRAMP
R1//R2 R9
1
Usually, R9 is 0Ω, though it can also be set
following equation 18 for better noise immunity. It
should also be less than 20% of R1//R2 to
VOUT VOUT VREF
2
(15)
R1
R2
VREF
minimize its influence on VRAMP
.
Where VOUT is the output ripple determined by
1 R1R2
equation 24.
(18)
R9
5 R1 R2
Setting the Output Voltage-Small ESR
Capacitors
Using equations 16 and 17 to calculate the
output voltage can be complicated. To simplify
the R1 calculation in equation 16, add a DC-
blocking capacitor, CDC, to filter the DC influence
from R4 and R9. Figure 12 shows a simplified
circuit with external ramp compensation and a
DC-blocking capacitor. The addition of this
capacitor, simplifies the R1 calculation as per
equation 19 for PWM mode operation.
SW
L
VOUT
R4
C4
R9
R1
R2
FB
Ceramic
Figure11—Simplified Ceramic Capacitor
Circuit
When using a low ESR ceramic capacitor on the
output, add an external voltage ramp
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
25
MPS [ MONOLITHIC POWER SYSTEMS ]
