MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
The worst-case condition occurs at VIN = 2VOUT
where:
,
1
2
VOUT VREF
VRAMP
(19)
R1
R2
1
2
IOUT
VREF
VRAMP
ICIN
(21)
2
For best results, select a CDC Value at least 10×
C4 for better DC blocking performance, but
smaller than 0.47µF account for start-up
performance. To use a larger CDC for better FB
noise immunity, reduce R1 and R2 to limit effects
on system start-up. Note that even with Cdc, the
For simplification, choose an input capacitor with
an RMS current rating that exceeds half the
maximum load current.
The input capacitance value determines the
converter input voltage ripple. Select a capacitor
value that meets any input voltage ripple
requirements.
load and line regulation are still related to VRAMP
.
SW
L
VOUT
Estimate the input voltage ripple as follows:
IOUT
VOUT
VOUT
(22)
V
(1
)
R4
C4
CDC
IN
FB
R1
R2
FSW CIN
V
V
IN
IN
Ceramic
The worst-case condition occurs at VIN = 2VOUT
where:
,
IOUT
4 FSW CIN
1
(23)
V
IN
Figure12—Simplified Ceramic Capacitor
Circuit with DC Blocking Capacitor
Output Capacitor
Input Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic capacitors or POSCAPs.
Estimate the output voltage ripple as:
The input current to the step-down converter is
discontinuous, and therefore, requires
a
capacitor to supply the AC current to the step-
down converter while maintaining the DC input
voltage. Use ceramic capacitors for best
performance. During layout, Place the input
capacitors as close to the IN pin as possible.
VOUT
V
1
VOUT
(1 OUT )(RESR
)
FSW L
V
8FSW COUT
IN
(24)
When using ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The capacitance also dominates the
output voltage ripple. For simplification, estimate
the output voltage ripple as:
The capacitance can vary significantly with
temperature. Use capacitors with X5R and X7R
ceramic dielectrics because they are fairly stable
over a wide temperature range.
VOUT
VOUT
(25)
The capacitors must also have a ripple current
rating that exceeds the converter’s maximum
input ripple current. Estimate the input ripple
current as follows:
VOUT
(1
)
8FSW2 L COUT
V
IN
The ESR only contributes minimally to the output
voltage ripple, thus requiring an external ramp to
stabilize the system. Design the external ramp
with R4 and C4 as per equation 5, 8 and 9.
VOUT
VOUT
(20)
ICIN IOUT
(1
)
V
V
IN
IN
MPQ8632 Rev.1.24
8/28/2013
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26
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