MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Where:
SW
FB
L
VOUT
(6)
(7)
IR4 IC4 IFB IC4
ESR
POSCAP
R1
R2
Then estimate the ramp on VFB as:
VIN VOUT
R4 C4
R1//R2
VRAMP
TON
R1//R2 R9
The VFB ripple’s descending slope then follows:
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
VRAMP
TOFF
VOUT
R4C4
(8)
VSLOPE1
To realize the stability without an external ramp,
usually select the ESR value as follows:
Equation 8 shows that if there is instability in
PWM mode, reduce either R4 or C4. If C4 is
irreducible due to equation 5 limitations, then
reduce R4. For a stable PWM operation, design
Vslope1 based on equation 9.
TSW
TON
2
0.7
(4)
RESR
COUT
TSW
TON
2
2LCOUT
Where TSW is the switching period.
RESR COUT
IOUT 103
TSW TON
0.7
(9)
VSLOPE1
VOUT
Ramp with a Small ESR Capacitor
Use an external ramp when using ceramic output
capacitors, because the ESR ripple is not high
enough to stabilize the system.
Where IOUT is the load current.
In skip mode, The VFB ripple’s descending slope
is almost same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
in skip mode when both the HS-FET and LS-FET
are off.
L
VOUT
SW
R4 C4
R1
R2
IR4
IC4
VOUT
R9
IFB
Ceramic
R1
FB
FB
ROUT
COUT
R2
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
Figure 8—Simplified Circuit in skip Mode
Figure 7 shows the simplified circuit in PWM
mode with the HS-FET OFF and an external
ramp compensation circuit (R4, C4). Design the
external ramp based on the inductor ripple
current. Select C4, R9, R1 and R2 to meet the
following condition:
Determine the VFB ripple’s descending slope in
skip mode as follows:
VREF
[(R1R2) // ROUT ]COUT
(10)
VSLOPE2
Where ROUT is the equivalent load resistor.
1
1
5
R1R2
R1R2
Figure 5 shows that VSLOPE2 in skip mode is lower
than that is in PWM mode, so it is
(5)
R9
2FSW C4
MPQ8632 Rev.1.24
8/28/2013
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