MP1527
2A, 1.3MHz
Step-Up Converter
Monolithic Power Systems
The fault time-out period is determined by the
equation:
minimum. Ceramic capacitors are preferred,
but tantalum or low-ESR electrolytic capacitors
may also suffice.
tFAULT = 6*105 * CSS
Use an input capacitor value greater than
4.7µF. The capacitor can be electrolytic,
tantalum or ceramic. However since it absorbs
the input switching current it requires an
adequate ripple current rating. Use a capacitor
with RMS current rating greater than the
inductor ripple current (see Selecting The
Inductor to determine the inductor ripple
current).
To insure stable operation place the input
capacitor as close to the IC as possible.
Alternately a smaller high quality ceramic
0.1µF capacitor may be placed closer to the IC
with the larger capacitor placed further away. If
using this technique, it is recommended that
If multiple MP1527 regulators are used in the
same circuit, the FAULT input/outputs can be
connected together. Should any one regulator
indicate a fault, it pulls all FAULT input/outputs
low, disabling all regulators. This insures that
all outputs are disabled should any one output
detect a fault. Pull-up FAULT to the input
voltage (IN) through a 100KΩ resistor. The
leakage current at FAULT is less than 250nA,
so up to 20 FAULT input/outputs can be
connected together through a single 100KΩ
pull-up resistor. To reduce current draw when
FAULT is active, a higher value pull-up resistor
may be used. Calculate the pull-up resistor
value by the equation:
the larger capacitor be
a
tantalum or
electrolytic type. All ceramic capacitors should
be placed close to the MP1527.
100kΩ ≤ RPULL-UP ≤ 2MΩ / N
Where N is the number of FAULT input/outputs
connected together.
Selecting the Output Capacitor
The output capacitor is required to maintain
the DC output voltage. Low ESR capacitors
are preferred to keep the output voltage ripple
to a minimum. The characteristic of the output
capacitor also affects the stability of the
regulation control system. Ceramic, tantalum,
or low ESR electrolytic capacitors are
recommended. In the case of ceramic
capacitors, the impedance of the capacitor at
the switching frequency is dominated by the
capacitance, and so the output voltage ripple is
mostly independent of the ESR. The output
voltage ripple is estimated to be:
Setting the Output Voltage
Set the output voltage by selecting the
resistive voltage divider ratio. The voltage
divider drops the output voltage to the 1.22V
feedback threshold voltage. Use 10KΩ for the
low-side resistor of the voltage divider.
Determine the high side resistor by the
equation:
RH = (VOUT - VFB) / (VFB / RL)
where RH is the high-side resistor, RL is the
low-side resistor, VOUT is the output voltage
and VFB is the feedback regulation threshold.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VIN
1-
×ILOAD
VOUT
VRIPPLE
≈
For RL = 10KΩ and VFB = 1.22V, then
RH (KΩ) = 8.20* (VOUT – 1.22V)
C2× fSW
Where VRIPPLE is the output ripple voltage, VIN
and VOUT are the DC input and output voltages
respectively, ILOAD is the load current, fSW is the
switching frequency, and C2 is the capacitance
of the output capacitor.
Selecting the Input Capacitor
An input capacitor is required to supply the AC
ripple current to the inductor, while limiting
noise at the input source. A low ESR capacitor
is required to keep the noise at the IC to a
In the case of tantalum or low-ESR electrolytic
capacitors, the ESR dominates the impedance
MP1527 Rev 1.8_8/31/05
Monolithic Power Systems, Inc.
9
MPS [ MONOLITHIC POWER SYSTEMS ]
