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XC68HC912D60FU8 参数 Datasheet PDF下载

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型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Central Processing Unit  
Indexed Addressing Modes  
2.6 Indexed Addressing Modes  
The CPU12 indexed modes reduce execution time and eliminate code  
size penalties for using the Y index register. CPU12 indexed addressing  
uses a postbyte plus zero, one, or two extension bytes after the  
instruction opcode. The postbyte and extensions do the following tasks:  
• Specify which index register is used.  
• Determine whether a value in an accumulator is used as an offset.  
• Enable automatic pre- or post-increment or decrement  
• Specify use of 5-bit, 9-bit, or 16-bit signed offsets.  
Table 2-2. Summary of Indexed Operations  
Source  
Code  
Syntax  
Postbyte  
Code (xb)  
Comments  
,r  
5-bit constant offset n = –16 to +15  
rr can specify X, Y, SP, or PC  
rr0nnnnn  
111rr0zs  
n,r  
–n,r  
Constant offset (9- or 16-bit signed)  
z-0 = 9-bit with sign in LSB of postbyte(s)  
1 = 16-bit  
if z = s = 1, 16-bit offset indexed-indirect (see below)  
rr can specify X, Y, SP, or PC  
n,r  
–n,r  
16-bit offset indexed-indirect  
rr can specify X, Y, SP, or PC  
111rr011  
rr1pnnnn  
[n,r]  
Auto pre-decrement/increment or Auto post-  
decrement/increment;  
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8  
n,–r n,+r  
n,r– n,r+  
rr can specify X, Y, or SP (PC not a valid choice)  
Accumulator offset (unsigned 8-bit or 16-bit)  
aa-00 = A  
01 = B  
10 = D (16-bit)  
11 = see accumulator D offset indexed-indirect  
rr can specify X, Y, SP, or PC  
A,r  
B,r  
D,r  
111rr1aa  
111rr111  
Accumulator D offset indexed-indirect  
rr can specify X, Y, SP, or PC  
[D,r]  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Advance Information  
35  
Central Processing Unit  
For More Information On This Product,  
Go to: www.freescale.com