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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Central Processing Unit  
Data Types  
Condition Code Register (CCR) contains five status indicators, two  
interrupt masking bits, and a STOP disable bit. The five flags are half  
carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The  
half-carry flag is used only for BCD arithmetic operations. The N, Z, V,  
and C status bits allow for branching based on the results of a previous  
operation.  
After a reset, the CPU fetches a vector from the appropriate address and  
begins executing instructions. The X and I interrupt mask bits are set to  
mask any interrupt requests. The S bit is also set to inhibit the STOP  
instruction.  
2.4 Data Types  
The CPU12 supports the following data types:  
• Bit data  
• 8-bit and 16-bit signed and unsigned integers  
• 16-bit unsigned fractions  
• 16-bit addresses  
A byte is eight bits wide and can be accessed at any byte location. A  
word is composed of two consecutive bytes with the most significant  
byte at the lower value address. There are no special requirements for  
alignment of instructions or operands.  
2.5 Addressing Modes  
Addressing modes determine how the CPU accesses memory locations  
to be operated upon. The CPU12 includes all of the addressing modes  
of the M68HC11 CPU as well as several new forms of indexed  
addressing. Table 2-1 is a summary of the available addressing modes.  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Advance Information  
Central Processing Unit  
33  
For More Information On This Product,  
Go to: www.freescale.com