Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
NOTE: The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event will result in a transmitter empty interrupt.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
17.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC)
Bit 7
0
6
0
5
IDAM1
0
4
IDAM0
0
3
0
2
1
Bit 0
CIDAC
$0108
R
IDHIT2
IDHIT1
IDHIT0
W
RESET
0
0
0
0
0
0
IDAM1 – IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organisation (see Identifier Acceptance Filter). Table 17-8
summarizes the different settings. In Filter Closed mode no
messages are accepted such that the foreground buffer is never
reloaded.
Table 17-9. Identifier Acceptance Mode Settings
IDAM1
IDAM0
Identifier Acceptance Mode
Two 32 bit Acceptance Filters
Four 16 bit Acceptance Filters
Eight 8 bit Acceptance Filters
Filter Closed
0
0
1
1
0
1
0
1
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
315
MSCAN Controller
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