Freescale Semiconductor, Inc.
Clock Functions
Limp-Home and Fast STOP Recovery modes
values before the clock loss. All clocks return to their normal settings and
Clock Monitor control is returned to the CME & FCME bits. If AUTO and
BCSP bits were set before the clock loss (selecting the PLL to provide a
system clock) the SYSCLK ramps-up and the PLL locks at the previously
selected frequency. To prevent PLL operation when the external clock
frequency comes back, software should clear the BCSP bit while running
in limp-home mode.
The two shaded regions A and B in Figure 12-3 present a of code run
away due to incorrect clocks on SYSCLK if the MCU is clocked by
EXTALi and the PLL is not used.
In region A, there is a delay between the loss of clock and its detection
by the clock monitor. When the EXTALi clock signal is disturbed, the
clock generation circuitry may receive an out of spec signal and drive the
CPU with irregular clocks. This may lead to code runaway.
In region B, as the 13-stage counter is free running, the count of 4096
may be reached when the amplitude of the EXTALi clock has not
stabilized. In this case, an improper EXTALi is sent to the clock
generation circuitry when limp-home mode is exited. This may also
cause code runaway.
If the MCU is clocked by the PLL, the risk of code runaway is very
low, but it can still occur under certain conditions due to irregular
clocks from the clock source appearing on the SYSCLK.
CAUTION: The COP watch dog should always be enabled in order to reset the MCU
in case of a code runaway situation.
NOTE: It is always advisable to take additional precautions within the
application software to trap such situations.
12.6.2 No Clock at Power-On Reset
The voltage level on VDDPLL determines how the MCU responds to an
external clock loss in this case.
With the VDDPLL supply voltage at VDD level, any reset sets the Clock
Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
151
Clock Functions
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