Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
Section 9. Resets and Interrupts
9.1 Contents
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .127
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.2 Introduction
CPU12 exceptions include resets and interrupts. Each exception has an
associated 16-bit vector, which points to the memory location where the
routine that handles the exception is located. Vectors are stored in the
upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Resets and Interrupts
123
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