Freescale Semiconductor, Inc.
Flash Memory
length of the erase pulse (t
), the erase margin pulse or pulses,
EPULSE
and the delay between turning off the high voltage and verifying the
operation (t ).
VERASE
Software also controls the supply of the proper program/erase voltage to
the V pin, and should be at the proper level before ENPE is set during
FP
a program/erase sequence.
A program/erase cycle should not be in progress when starting another
program/erase, or while attempting to read from the array.
NOTE: Although clearing ENPE disables the program/erase voltage (V ) from
FP
the V pin to the array, care must be taken to ensure that V is at V
FP
FP
DD
whenever programming/erasing is not in progress. Not doing so could
damage the part. Ensuring that V is always greater or equal to V
FP
DD
can be accomplished by controlling the V power supply with the
FP
programming software via an output pin. Alternatively, all programming
and erasing can be done prior to installing the device on an application
circuit board which can always connect V to V . Programming can
FP
DD
also be accomplished by plugging the board into a special programming
fixture which provides program/erase voltage to the V pin.
FP
7.8 Programming the Flash EEPROM
Programming the Flash EEPROM is accomplished by the following
sequence. The V pin voltage must be at the proper level prior to
FP
executing step 4 the first time.
1. Apply program/erase voltage to the V pin.
FP
2. Clear ERAS and set the LAT bit in the FEExxCTL register to
establish program mode and enable programming address and
data latches.
3. Write data to a valid address. The address and data is latched. If
BOOTP is asserted, an attempt to program an address in the boot
block will be ignored.
4. Apply programming voltage by setting ENPE.
5. Delay for one programming pulse (t
).
PPULSE
Advance Information
108
68HC(9)12D60 — Rev 4.0
MOTOROLA
Flash Memory
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MOTOROLA [ MOTOROLA ]
