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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Flash Memory  
Bit 7  
0
6
0
0
5
0
0
4
FEESWAI  
0
3
SVFP  
0
2
ERAS  
0
1
LAT  
0
Bit 0  
ENPE  
0
RESET:  
0
FEE32CTL/FEE28CTL — Flash EEPROM Control Register  
$00F7/$00FB  
This register controls the programming and erasure of the Flash  
EEPROM.  
FEESWAI — Flash EEPROM Stop in Wait Control  
0 = Do not halt Flash EEPROM clock when the part is in wait mode.  
1 = Halt Flash EEPROM clock when the part is in wait mode.  
NOTE: The FEESWAI bit cannot be asserted if the interrupt vector resides in the  
Flash EEPROM array.  
SVFP — Status V Voltage  
FP  
SVFP is a read only bit.  
0 = Voltage of V pin is below normal programming voltage levels  
FP  
1 = Voltage of V pin is above normal programming voltage levels  
FP  
ERAS — Erase Control  
This bit can be read anytime or written when ENPE = 0. When set, all  
locations in the array will be erased at the same time. The boot block  
will be erased only if BOOTP = 0. This bit also affects the result of  
attempted array reads. See Table 7-1 for more information. Status of  
ERAS cannot change if ENPE is set.  
0 = Flash EEPROM configured for programming  
1 = Flash EEPROM configured for erasure  
LAT — Latch Control  
This bit can be read anytime or written when ENPE = 0. When set, the  
Flash EEPROM is configured for programming or erasure and, upon  
the next valid write to the array, the address and data will be latched  
for the programming sequence. See Table 7-1 for the effects of LAT  
Advance Information  
104  
68HC(9)12D60 — Rev 4.0  
Flash Memory  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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