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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Flash Memory  
Bit 7  
6
GADR  
0
5
HVT  
0
4
FENLV  
0
3
FDISVFP  
0
2
VTCK  
0
1
STRE  
0
Bit 0  
MWPR  
0
FSTE  
RESET:  
0
FEE32TST/FEE28TST — Flash EEPROM Module Test Register  
$00F6/$00FA  
In normal mode, writes to FEETST control bits have no effect and always  
read zero. The Flash EEPROM module cannot be placed in test mode  
inadvertently during normal operation.  
FSTE — Stress Test Enable  
0 = Disables the gate/drain stress circuitry  
1 = Enables the gate/drain stress circuitry  
GADR — Gate/Drain Stress Test Select  
0 = Selects the drain stress circuitry  
1 = Selects the gate stress circuitry  
HVT — Stress Test High Voltage Status  
0 = High voltage not present during stress test  
1 = High voltage present during stress test  
FENLV — Enable Low Voltage  
0 = Disables low voltage transistor in current reference circuit  
1 = Enables low voltage transistor in current reference circuit  
FDISVFP — Disable Status V Voltage Lock  
FP  
When the V pin is below normal programming voltage the Flash  
FP  
module will not allow writing to the LAT bit; the user cannot erase or  
program the Flash module. The FDISVFP control bit enables writing  
to the LAT bit regardless of the voltage on the V pin.  
FP  
0 = Enable the automatic lock mechanism if V is low  
FP  
1 = Disable the automatic lock mechanism if V is low  
FP  
Advance Information  
102  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Flash Memory  
For More Information On This Product,  
Go to: www.freescale.com  
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