欢迎访问ic37.com |
会员登录 免费注册
发布采购

UC3844 参数 Datasheet PDF下载

UC3844图片预览
型号: UC3844
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能电流模式控制器 [HIGH PERFORMANCE CURRENT MODE CONTROLLERS]
分类和应用: 控制器
文件页数/大小: 14 页 / 380 K
品牌: MOTOROLA [ MOTOROLA ]
 浏览型号UC3844的Datasheet PDF文件第5页浏览型号UC3844的Datasheet PDF文件第6页浏览型号UC3844的Datasheet PDF文件第7页浏览型号UC3844的Datasheet PDF文件第8页浏览型号UC3844的Datasheet PDF文件第10页浏览型号UC3844的Datasheet PDF文件第11页浏览型号UC3844的Datasheet PDF文件第12页浏览型号UC3844的Datasheet PDF文件第13页  
UC3844, 45 UC2844, 45  
Undervoltage Lockout  
added flexibility in tailoring the drive voltage independent of  
A zener clamp is typically connected to this input when  
V
Two undervoltage lockout comparators have been  
incorporated to guartantee that the IC is fully functional before  
the output stage is enabled. The positive power supply  
CC.  
driving power MOSFETs in systems where V  
is greater the  
CC  
20 V. Figure 22 shows proper power and control ground  
connections in a current sensing power MOSFET  
application.  
terminal (V  
and the reference output (V ) are each  
CC  
ref  
monitored by separate comparators. Each has built–in  
hysteresis to prevent erratic output behavior as their  
Reference  
respective thresholds are crossed. The V  
comparator  
CC  
upper and lower thresholds are 16 V/10 V for the UCX844,  
and 8.4 V/7.6 V for the UCX845. The V comparator upper  
The 5.0 V bandgap reference is trimmed to ± 1.0%  
tolerance at T = 25°C on the UC284X, and ± 2.0% on the  
J
ref  
UC384X. Its primary purpose is to supply charging current to  
the oscillator timing capacitor. The reference has short circuit  
protection and is capable of providing in excess of 20 mA for  
powering additional control system circuitry.  
and lower thresholds are 3.6 V/3/4 V. The large hysteresis  
and low startup current of the UCX844 makes it ideally suited  
in off–line converter applications where efficient bootstrap  
startup techniques later required (Figure 29). The UCX845 is  
intended for lower voltage dc–to–dc converter applications. A  
Design Considerations  
36 V zener is connected as a shunt regulator from V  
to  
CC  
Do not attempt to construct the converter on  
wire–wrap or plug–in prototype boards. High frequency  
circuit layout techniques are imperative to prevent pulsewidth  
jitter. This is usually caused by excessive noise pick–up  
imposed on the Current Sense or Voltage Feedback inputs.  
Noise immunity can be improved by lowering circuit  
impedances at these points. The printed circuit layout should  
contain a ground plane with low–current signal and  
high–current switch and output grounds returning on  
separate paths back to the input filter capacitor. Ceramic  
ground. Its purpose is to protect the IC from excessive  
voltage that can occur during system startup. The minimum  
operating voltage for the UCX844 is 11 V and 8.2 V for the  
UCX845.  
Output  
These devices contain a single totem pole output stage  
that was specifically designed for direct drive of power  
MOSFETs. It is capable of up to ± 1.0 A peak drive current  
and has a typical rise and fall time of 50 ns with a 1.0 nF load.  
Additional internal circuitry has been added to keep the  
Output in a sinking mode whenever and undervoltage lockout  
is active. This characteristic eliminates the need for an  
external pull–down resistor.  
bypass capacitors (0.1 µF) connected directly to V , V ,  
CC  
C
and V may be required depending upon circuit layout. This  
ref  
provides a low impedance path for filtering the high frequency  
noise. All high current loops should be kept as short as  
possible using heavy copper runs to minimize radiated EMI.  
The Error Amp compensation circuitry and the converter  
output voltage divider should be located close to the IC and  
as far as possible from the power switch and other noise  
generating components.  
The SO–14 surface mount package provides separate  
pins for V (output supply) and Power Ground. Proper  
C
implementation will significantly reduce the level of switching  
transient noise imposed on the control circuitry. This  
becomesparticularlyusefulwhenreducingtheI  
clamp  
pk(max)  
level. The separate V supply input allows the designer  
C
Figure 18. External Duty Cycle Clamp and  
Multi–Unit Synchronization  
Figure 17. External Clock Synchronization  
V
ref  
8(14)  
R
R
8(14)  
R
R
Bias  
R
R
A
R
T
Bias  
4
8
B
5.0k  
6
Osc  
+
External  
Sync  
Input  
Osc  
+
4(7)  
R
S
C
T
3
0.01  
+
4(7)  
5
2
Q
+
+
+
2R  
R
7
EA  
47  
2(3)  
1(1)  
2R  
R
5.0k  
1
EA  
2(3)  
1(1)  
C
MC1455  
5(9)  
5(9)  
To Additional  
UCX84XA’s  
R
B
1.44  
(R + 2R )C  
The diode clamp is required if the Sync amplitude is large enough to  
cause the bottom side of CT to go more than 300 mV below ground.  
f =  
D
=
max  
R
+ 2R  
B
A
B
A
9
MOTOROLA ANALOG IC DEVICE DATA