S0
S1
S2
S3
S4
S5
S6
S7
CLK
6A
FC2–FC0
8
6
A23–A0
AS
7
12
15
14
11
11A
13
17
LDS / UDS
R/W
9
18
28
47
DTACK
27
31
48
29
DATA IN
47
30
BERR / BR
(NOTE 2)
47
47
32
32
56
HALT / RESET
47
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the
next falling edge of the clock.
2. BR need fall at this time only to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 V and 2.0 V.
Figure 9. MC68SEC000 Read Cycle Timing Diagram
M68000 USER’S MANUAL ADDENDUM
14
MOTOROLA