STROBES
AND R/W
36
BR
35
34
39
BG
33
38
CLK
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA
guarantees their recognition at the next falling edge of the clock.
Figure 11. Bus Arbitration Timing
CLK
47
33
BR
BG
34
35
36
39
58
38
AS
LDS/UDS
DS
R/W
58A
FC2–FC0
A23
A19–A0
D15
D7–D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
Figure 12. MC68SEC000 Bus Arbitration Timing Diagram
MOTOROLA
M68000 USER’S MANUAL ADDENDUM
17