6.3.1.1 Control Registers
Control registers contain parameters for configuring the QSPI and enabling various
modes of operation. The CPU has read and write access to all control registers, but
the QSM has read-only access to all bits except the SPE bit in SPCR1. Control regis-
ters must be initialized before the QSPI is enabled to ensure defined operation.
SPCR1 must be written last because it contains the QSPI enable bit (SPE).
Writing a new value to any control register except SPCR2 while the QSPI is enabled
disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after
completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execu-
tion to restart at the designated location. Reads of SPCR2 return the current value of
the register, not of the buffer.
Writing the same value into any control register except SPCR2 while the QSPI is en-
abled has no effect on QSPI operation.
6.3.1.2 Status Register
The QSPI status register (SPSR) contains information concerning the current serial
transmission. Only the QSPI can set the bits in this register. The CPU reads the SPSR
to obtain QSPI status information and writes it to clear status flags.
6
6.3.2 QSPI RAM
The QSPI contains an 80-byte block of dual-access static RAM that can be accessed
by both the QSPI and the CPU. The RAM is divided into three segments: receive data
RAM, transmit data RAM, and command control data RAM. Receive data is informa-
tion received from a serial device external to the MCU. Transmit data is information
stored by the CPU for transmission to an external device. Command control data is
used to perform transfers. Refer to Figure 6-3, which shows RAM organization.
D00
RR0
RR1
RR2
D20
TR0
TR1
TR2
D40
CR0
CR1
CR2
RECEIVE
RAM
TRANSMIT
RAM
COMMAND
RAM
RRD
RRE
RRF
TRD
TRE
TRF
CRD
CRE
CRF
D1E
D3E
D4F
WORD
WORD
BYTE
QSPI RAM MAP
Figure 6-3 QSPI RAM
MC68331
QUEUED SERIAL MODULE
MOTOROLA
6-7
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
