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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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6.2.2 QSM Pin Control Registers  
The QSM uses nine pins. Eight of the pins can be used for serial communication or for  
parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns  
the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.  
PQSPAR does not affect operation of the SCI.  
The port QS data direction register (DDRQS) determines whether pins are inputs or  
outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the  
pin an output. DDRQS affects both QSPI function and I/O function. DDQS1 deter-  
mines the direction of the TXD pin only when the SCI transmitter is disabled. When the  
SCI transmitter is enabled, the TXD pin is an output. PQSPAR and DDRQS are 8-bit  
registers located at the same word address. Table 6-1 is a summary of QSM pin func-  
tions.  
The port QS data register (PORTQS) latches I/O data. Writes to PORTQS drive pins  
defined as outputs. PORTQS reads return data present on the pins when the read is  
made. To avoid driving undefined data, first write PORTQS, then configure DDRQS.  
Table 6-1 QSM Pin Function  
6
QSM Pin  
Mode  
DDRQS Bit  
Bit  
State  
Pin Function  
MISO  
Master  
DDQS0  
0
1
Serial Data Input to QSPI  
Disables Data Input  
Slave  
Master  
Slave  
0
Disables Data Output  
Serial Data Output from QSPI  
Disables Data Output  
Serial Data Output from QSPI  
Serial Data Input to QSPI  
Disables Data Input  
1
MOSI  
DDQS1  
DDQS2  
0
1
0
1
1
SCK  
Master  
Slave  
0
Disables Clock Output  
Clock Output from QSPI  
Clock Input to QSPI  
1
0
1
Disables Clock Input  
Assertion Causes Mode Fault  
Chip-Select Output  
PCS0/SS  
PCS[3:1]  
Master  
Slave  
DDQS3  
0
1
0
QSPI Slave Select Input  
Disables Select Input  
Disables Chip-Select Output  
Chip-Select Output  
1
Master  
Slave  
DDQS[4:6]  
0
1
0
Inactive  
1
Inactive  
2
TXD  
Transmit  
Receive  
DDQS7  
None  
X
NA  
Serial Data Output from SCI  
Serial Data Input to SCI  
RXD  
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes the SPI  
serial clock SCK.  
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 set), in which case it becomes  
SCI serial output TXD and DDRQS has no effect.  
MOTOROLA  
6-4  
QUEUED SERIAL MODULE  
MC68331  
USER’S MANUAL