QUEUE CONTROL
BLOCK
4
QUEUE
POINTER
COMPARATOR
DONE
END QUEUE
POINTER
80-BYTE
QSPI RAM
ADDRESS
REGISTER
4
CONTROL
LOGIC
STATUS
REGISTER
CONTROL
REGISTERS
6
CHIP SELECT
COMMAND
4
4
DELAY
COUNTER
M
S
MSB
LSB
8/16-BIT SHIFT REGISTER
Rx/Tx DATA REGISTER
MOSI
MISO
PROGRAMMABLE
LOGIC ARRAY
M
S
PCS0/SS
PCS [3:1]
3
BAUD RATE
GENERATOR
SCK
QSPI BLOCK
Figure 6-2 QSPI Block Diagram
6.3.1 QSPI Registers
The programmer's model for the QSPI consists of the QSM global and pin control reg-
isters, four QSPI control registers (SPCR[0:3]), a status register (SPCR), and the 80-
byte QSPI RAM.
Registers and RAM can be read and written by the CPU. Refer to APPENDIX D REG-
ISTER SUMMARY for register bit and field definitions.
MOTOROLA
6-6
QUEUED SERIAL MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
