Table 4-10 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
Byte
0
1
1
0
1
0
1
0
Word
3 Byte
Long Word
4.4.1.7 Function Codes
The CPU generates function code output signals FC[2:0] to indicate the type of activity
occurring on the data or address bus. These signals can be considered address ex-
tensions that can be externally decoded to determine which of eight external address
spaces is accessed during a bus cycle.
Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 4-11 shows address space encoding.
4
Table 4-11 Address Space Encoding
FC2
0
FC1
0
FC0
0
Address Space
Reserved
0
0
1
User Data Space
User Program Space
Reserved
0
1
0
0
1
1
1
0
0
Reserved
1
0
1
Supervisor Data Space
Supervisor Program Space
CPU Space
1
1
0
1
1
1
The supervisor bit in the status register determines whether the CPU is operating in
supervisor or user mode. Addressing mode and the instruction being executed deter-
mine whether a memory access is to program or data space.
4.4.1.8 Data and Size Acknowledge Signals
During normal bus transfers, external devices assert the data and size acknowledge
signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig-
nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
to 4.8 Chip Selects for more information.
4.4.1.9 Bus Error Signal
The bus error signal BERR is asserted when a bus cycle is not properly terminated by
DSACK or AVEC assertion. BERR can also be asserted at the same time as DSACK,
provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Exception
Control Cycles for more information.
MC68331
SYSTEM INTEGRATION MODULE
MOTOROLA
4-19
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
