The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-
icant operand word is transferred on the first bus cycle and the least significant oper-
and word is transferred on a following bus cycle.
4.4.5 Operand Transfer Cases
Table 4-13 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus
cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following
paragraphs discuss all the allowable transfer cases in detail.
Table 4-13 Operand Transfer Cases
Read Cycles
Write Cycles
Num
Transfer Case
SIZ ADDR0 DSACK DATA DATA DATA DATA
Next
Cycle
[1:0]
01
01
01
10
10
10
10
00
10
00
10
11
11
[1:0]
10
01
01
10
10
11
01
10
10
01
01
10
10
[15:8]
OP0
OP0
—
[7:0]
—
[15:8]
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
[7:0]
(OP0)
(OP0)
OP0
1
2
3
4
5
6
7
8
9
Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
X
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
1
—
OP0
—
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
OP0
OP0
OP0
—
(OP1)
(OP0)
OP1
1
—
1
4
OP1
OP0
—
—
2
1
Word to 16-Bit Port (Misaligned)
OP0
Long Word to 8-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)
OP0
OP0
OP0
—
(OP1)
(OP0)
OP1
13
12
6
1
—
10 Long Word to 16-Bit Port (Aligned)
OP1
OP0
—
1
11 Long Word to 16-Bit Port (Misaligned)
OP0
2
2
12 3 Byte to 8-Bit Port (Aligned)
OP0
OP0
(OP1)
(OP0)
5
2
13 3 Byte to 8-Bit Port (Misaligned)
—
4
1. The CPU32 does not support misaligned transfers.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
4.5 Bus Operation
Internal microcontroller modules are typically accessed in two system clock cycles,
with no wait states. Regular external bus cycles use handshaking between the MCU
and external peripherals to manage transfer size and data. These accesses take three
system clock cycles, again with no wait states. During regular cycles, wait states can
be inserted as needed by bus control logic. Refer to 4.5.2 Regular Bus Cycles for
more information.
Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Chip-select logic can
also be used to insert wait states before internal generation of handshaking signals.
Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information.
Bus control signal timing, as well as chip-select signal timing, are specified in APPEN-
DIX A ELECTRICAL CHARACTERISTICS. Refer to the SIM Reference Manual (SIM-
RM/AD) for more information about each type of bus cycle.
The MCU is responsible for de-skewing signals it issues at both the start and the end
of a cycle. In addition, the MCU is responsible for de-skewing acknowledge and data
signals from peripheral devices.
MOTOROLA
4-22
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
