$000000
$000000
VECTOR VECTOR
OFFSET NUMBER
TYPE OF
EXCEPTION
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0
1
2
3
4
5
6
7
8
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
$XX0000
9
10
11
12
13
14
15
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
0040–005C 16–23
006C
0064
0068
006C
0070
0074
0078
007C
24
25
26
27
28
29
30
31
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
SUPERVISOR
SPACE
USER
SPACE
0080–00BC 32–47
00C0–00EB 48–58
00EC–00FC 59–63
0100–03FC 64–255
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX03FC
3
$YFF000
$YFF900
GPT
4
$7FF000
$7FF000
$YFF93F
$YFFA00
INTERNAL REGISTERS
INTERNAL REGISTERS
RESERVED
SIM
$YFFA7F
$YFFA80
$YFFAFF
RESERVED
$YFFC00
QSM
$YFFDFF
4
$FF0000
$FFFFFF
$FF0000
$FFFFFF
INTERNAL REGISTERS
INTERNAL REGISTERS
$YFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
331 S/U SEP MAP
Figure 3-6 Separate Supervisor and User Space Map
MC68331
USER’S MANUAL
OVERVIEW
MOTOROLA
3-13
MOTOROLA [ MOTOROLA ]
