Table 3-5 Signal Function (Continued)
Signal Name
Data Strobe
Mnemonic
Function
DS
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
Data and Size Acknowledge
DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing
Development Serial In, Out, Clock
DSI, DSO,
DSCLK
Serial I/O and clock for background debugging mode
Crystal Oscillator
EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
Function Codes
Freeze
FC[2:0]
FREEZE
HALT
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
Halt
Input Capture
IC[3:1]
When a specified transition is detected on an input capture pin, the
value in an internal GPT counter is latched
Input Capture 4/
IC4/OC5
Can be configured for either an input capture or output compare
Output Compare 5
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
IPIPE, IFETCH Indicate instruction pipeline activity
IRQ[7:1]
MISO
Provides an interrupt priority level to the CPU
Serial input to QSPI in master mode; serial output from QSPI in
slave mode
Clock Mode Select
Master Out Slave In
MODCLK
MOSI
Selects the source and type of system clock
3
Serial output from QSPI in master mode; serial input to QSPI in
slave mode
Output Compare
OC[5:1]
Change state when the value of an internal GPT counter matches
a value stored in a GPT control register
Pulse Accumulator Input
Port C
PAI
Signal input to the pulse accumulator
SIM digital output port signals
External clock dedicated to the GPT
QSPI peripheral chip selects
SIM digital I/O port signals
PC[6:0]
PCLK
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
PCS[3:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
Port F
SIM digital I/O port signals
Port GP
GPT digital I/O port signals
Port QS
QSM digital I/O port signals
Pulse-Width Modulation
Quotient Out
PWMA, PWMB Output for PWM
QUOT
RESET
RMC
R/W
Provides the quotient bit of the polynomial divider
Reset
System reset
Read-Modify-Write Cycle
Read/Write
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
Serial input to the SCI
SCI Receive Data
QSPI Serial Clock
RXD
SCK
Clock output from QSPI in master mode; clock input to QSPI in
slave mode
Size
SIZ[1:0]
SS
Indicates the number of bytes to be transferred during a bus cycle
Slave Select
Causes serial transmission when QSPI is in slave mode; causes
mode fault in master mode
Three-State Control
SCI Transmit Data
TSC
TXD
XFC
Places all output drivers in a high-impedance state
Serial output from the SCI
External Filter Capacitor
Connection for external phase-locked loop filter capacitor
MC68331
OVERVIEW
MOTOROLA
3-9
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
