Table A-9 QSPI Timing
(V = 5.0 V ± 10%, V = 0 Vdc, T = T to T , 200 pF load on all QSPI pins)
DD
dc
SS
A
L
H
Num
Function
Operating Frequency
Symbol
Min
Max
Unit
f
op
Master
Slave
DC
DC
1/4
1/4
System Clock Frequency
System Clock Frequency
1
2
3
4
5
6
7
Cycle Time
Master
t
qcyc
4
4
510
—
t
t
cyc
cyc
Slave
Enable Lead Time
Master
t
lead
2
2
128
—
t
t
cyc
cyc
Slave
Enable Lag Time
Master
t
lag
—
2
1/2
—
SCK
Slave
t
cyc
Clock (SCK) High or Low Time
Master
t
sw
2 t – 60
255 t
—
ns
ns
cyc
cyc
2
Slave
2 t – n
cyc
Sequential Transfer Delay
Master
t
td
17
13
8192
—
t
t
cyc
cyc
Slave (Does Not Require Deselect)
A
Data Setup Time (Inputs)
t
su
Master
Slave
30
20
—
—
ns
ns
Data Hold Time (Inputs)
t
hi
Master
Slave
0
20
—
—
ns
ns
8
9
Slave Access Time
t
—
—
1
2
t
a
cyc
cyc
Slave MISO Disable Time
t
t
dis
10 Data Valid (after SCK Edge)
t
v
Master
Slave
—
—
50
50
ns
ns
11 Data Hold Time (Outputs)
t
ho
Master
Slave
0
0
—
—
ns
ns
12 Rise Time
3
Input
Output
t
—
—
2
30
µs
ns
ri
t
ro
13 Fall Time
3
Input
Output
t
—
—
2
30
µs
ns
fi
t
fo
Notes:
1 All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. In formula, n = External SCK rise + External SCK fall time
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sources
are at valid V /V prior to SCK transitioning between valid V and V . Due to process variation, logic decision
OH OL
OL
OH
point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used.
MOTOROLA
A-24
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
