Table A-8 16.78 MHz ECLK Bus Timing
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
E1
E2
E3
E4
E5
E6
E7
E8
E9
Characteristic
Symbol
Min
Max
60
—
150
—
—
—
—
60
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
ECLK Low to Address Valid
t
t
—
15
—
EAD
EAH
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
15
30
30
5
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
—
EDHZ
ECDH
t
0
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
t
—
t
t
ECDZ
cyc
cyc
t
—
2
EDDW
EDHW
t
15
386
296
1/2
—
—
—
—
ns
ns
ns
3
E13 Address Access Time (Read)
t
EACC
A
4
E14 Chip Select Access Time (Read)
t
EACS
E15 Address Setup Time
t
t
cyc
EAS
Table A-8a 20.97 MHz ECLK Bus Timing
(V = 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
E1
E2
E3
E4
E5
E6
E7
E8
E9
Characteristic
Symbol
Min
—
Max
48
—
120
—
—
—
—
48
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
ECLK Low to Address Valid
t
t
EAD
EAH
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
10
—
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
10
25
25
5
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
—
EDHZ
ECDH
t
0
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
t
—
t
t
ECDZ
cyc
cyc
t
t
—
2
EDDW
EDHW
10
308
236
1/2
—
—
—
—
ns
ns
ns
3
E13 Address Access Time (Read)
t
EACC
4
E14 Chip Select Access Time (Read)
t
EACS
E15 Address Setup Time
t
t
cyc
EAS
Notes for Tables A–8 and A–8a:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
.
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
MOTOROLA
A-22
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL