MC145152–2 BLOCK DIAGRAM
RA2
RA1
RA0
12 x 8 ROM REFERENCE DECODER
12
OSC
out
LOCK
DETECT
LD
OSC
in
12–BIT
÷
R COUNTER
MC
φ
V
CONTROL
LOGIC
PHASE
DETECTOR
φ
R
f
in
6–BIT
A5
÷
A COUNTER
10–BIT
N2
÷
N COUNTER
A3 A2
A0
N0
N4 N5
N7
N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
Prescaling section). The A inputs all have internal pull–up
resistors that ensure that inputs left open will remain at a
logic 1.
PIN DESCRIPTIONS
INPUT PINS
f
in
OSC , OSC
in
out
Frequency Input (Pin 1)
Reference Oscillator Input/Output (Pins 27, 26)
Input to the positive edge triggered ÷ N and ÷ A counters.
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
f
is typically derived from a dual–modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
in
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
ated reference signal. This signal is typically ac coupled to
OSC , but for larger amplitude signals (standard CMOS
in
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The
total reference divide values are as follows:
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
.
out
OUTPUT PINS
Total
Divide
Value
Reference Address Code
φ , φ
R
V
RA2
RA1
RA0
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally
for a loop–error signal.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
If the frequency f is greater than f or if the phase of f is
128
256
512
1024
1160
2048
V
R
V
leading, then error information is provided by φ pulsing low.
φ
R
V
remains essentially high.
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
φ
V
remains essentially high.
If the frequency of f = f and both are in phase, then both
and φ remain high except for a small minimum time
R
period when both pulse low in phase.
V
R
N0 – N9
φ
V
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the ÷ N
counter when it reaches the count of 0. N0 is the least signifi-
cant digit and N9 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
a SPST switch to alter data to the zero state.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first
A0 – A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of f that
in
require a logic 0 on the MC output (see Dual–Modulus
MC145151–2 through MC145158–2
6
MOTOROLA
MOTOROLA [ MOTOROLA ]
