Table 1. Partial List of Crystal Manufacturers
Address
Name
Phone
United States Crystal Corp.
Crystek Crystal
Statek Corp.
3605 McCart Ave., Ft. Worth, TX 76110
2351 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
(817) 921–3013
(813) 936–2109
(714) 639–7810
NOTE: Motorolacannotrecommendonesupplieroveranotherandinnowaysuggeststhatthisisacomplete
listing of crystal manufacturers.
N is the number programmed into the ÷ N counter, A is the
number programmed into the ÷ A counter, P and P + 1 are
the two selectable divide ratios available in the dual–modu-
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2 Feb.,
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
lus prescalers. To have a range of N values in sequence,
T
the ÷ A counter is programmed from zero through P – 1 for a
particular value N in the ÷ N counter. N is then incremented to
N + 1 and the ÷ A is sequenced from 0 through P – 1 again.
There are minimum and maximum values that can be
achieved for N . These values are a function of P and the
T
size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If A
= P – 1, then
max
= (P – 1) P + A or (P – 1) P since A
N
≥ P – 1. Then N
min
Tmin
DUAL–MODULUS PRESCALING
OVERVIEW
is free to assume the value of 0.
N
= N
P+ A
max
Tmax
max
The technique of dual–modulus prescaling is well estab-
lished as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable
counters to be used as high–frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and per-
formance that results if a fixed (single–modulus) divider is
used for the prescaler.
In dual–modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is neces-
sary to select the divide value P or P + 1 in the prescaler for
the required amount of time (see modulus control definition).
Motorola’s dual–modulus frequency synthesizers contain
this feature and can be used with a variety of dual–modulus
prescalers to allow speed, complexity and cost to be tailored
to the system requirements. Prescalers having P, P + 1 di-
vide values in the range of ÷ 3/÷ 4 to ÷ 128/÷ 129 can be con-
trolled by most Motorola frequency synthesizers.
To maximize system frequency capability, the dual–modu-
lus prescaler output must go from low to high after each
group of P or P + 1 input cycles. The prescaler should divide
by P when its modulus control line is high and by P + 1 when
its MC is low.
For the maximum frequency into the prescaler (f
VCOmax
the value used for P must be large enough such that:
),
1. f
divided by P may not exceed the frequency
VCOmax
capability of f (input to the ÷ N and ÷ A counters).
in
2. The period of f
divided by P must be greater than
VCO
the sum of the times:
a. Propagation delay through the dual–modulus pre-
scaler.
b. Prescaler setup or release time relative to its MC
signal.
c. Propagation time from f to the MC output for the
in
frequency synthesizer device.
Several dual–modulus prescaler approaches suitable for
use with the MC145152–2, MC145156–2, or MC145158–2
are:
A sometimes useful simplification in the programming
code can be achieved by choosing the values for P of 8, 16,
32, or 64. For these cases, the desired value of N results
T
when N in binary is used as the program code to the ÷ N and
T
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12022A
MC12032A
÷ 5/÷ 6
÷ 8/÷ 9
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
2.0 GHz
÷ A counters treated in the following manner:
a
1. Assume the ÷ A counter contains “a” bits where 2 ≥ P.
÷ 10/÷ 11
÷ 32/÷ 33
2. Always program all higher order ÷ A counter bits above
“a” to 0.
÷ 40/÷ 41
÷ 64/÷ 65
3. Assume the ÷ N counter and the ÷ A counter (with all the
higher order bits above “a” ignored) combined into a
single binary counter of n + a bits in length (n = number
of divider stages in the ÷ N counter). The MSB of this “hy-
pothetical”counter is to correspond to the MSB of ÷ Nand
the LSB is to correspond to the LSB of ÷ A. The system
divide value, N , now results when the value of N in
÷ 128/÷ 129
÷ 64/65 or ÷ 128/129
÷ 64/65 or ÷ 128/129
DESIGN GUIDELINES
The system total divide value, N
the application:
(N ) will be dictated by
T
total
T
T
binary is used to program the “new” n + a bit counter.
frequency into the prescaler
By using the two devices, several dual–modulus values
are achievable (shown in Figure 13).
N
=
= N P + A
T
frequency into the phase detector
MC145151–2 through MC145158–2
30
MOTOROLA
MOTOROLA [ MOTOROLA ]
