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MC145151DW2 参数 Datasheet PDF下载

MC145151DW2图片预览
型号: MC145151DW2
PDF下载: 下载PDF文件 查看货源
内容描述: 并行输入锁相环频率合成器 [Parallel-Input PLL Frequency Synthesizer]
分类和应用: 信号电路锁相环或频率合成电路光电二极管
文件页数/大小: 36 页 / 718 K
品牌: MOTOROLA [ MOTOROLA ]
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CRYSTAL OSCILLATOR CONSIDERATIONS  
C
values. The shunt load capacitance, C , presented  
L L  
across the crystal can be estimated to be:  
The following options may be considered to provide a ref-  
erence frequency to Motorola’s CMOS frequency synthe-  
sizers.  
C C  
C1 C2  
in out  
C =  
L
+ C + C +  
a o  
C
+ C  
C1 + C2  
in  
out  
where  
Use of a Hybrid Crystal Oscillator  
C
= 5 pF (see Figure 11)  
= 6 pF (see Figure 11)  
C = 1 pF (see Figure 11)  
in  
out  
a
O
C
Commercially available temperature–compensated crystal  
oscillators (TCXOs) or crystal–controlled data clock oscilla-  
tors provide very stable reference frequencies. An oscillator  
capable of sinking and sourcing 50 µA at CMOS logic levels  
C
= the crystal’s holder capacitance  
(see Figure 12)  
C1 and C2 = external capacitors (see Figure 10)  
may be direct or dc coupled to OSC . In general, the highest  
frequency capability is obtained utilizing a direct–coupled  
in  
C
a
square wave having a rail–to–rail (V  
swing. If the oscillator does not have CMOS logic levels on  
the outputs, capacitive or ac coupling to OSC may be used.  
to V ) voltage  
DD  
SS  
in  
C
C
out  
in  
OSC , an unbuffered output, should be left floating.  
out  
For additional information about TCXOs and data clock  
oscillators, please consult the latest version of the eem Elec-  
tronic Engineers Master Catalog, the Gold Book, or similar  
publications.  
Figure 11. Parasitic Capacitances of the Amplifier  
R
L
C
S
S
S
Design an Off–Chip Reference  
1
2
1
2
The user may design an off–chip crystal oscillator using  
ICs specifically developed for crystal oscillator applications,  
such as the MC12061 MECL device. The reference signal  
C
O
from the MECL device is ac coupled to OSC . For large am-  
plitude signals (standard CMOS logic levels), dc coupling is  
in  
R
X
e
e
2
1
used. OSC , an unbuffered output, should be left floating.  
out  
In general, the highest frequency capability is obtained with a  
direct–coupled square wave having rail–to–rail voltage  
swing.  
NOTE: Values are supplied by crystal manufacturer  
(parallel resonant crystal).  
Figure 12. Equivalent Crystal Networks  
Use of the On–Chip Oscillator Circuitry  
The on–chip amplifier (a digital inverter) along with an ap-  
propriate crystal may be used to provide a reference source  
frequency. A fundamental mode crystal, parallel resonant at  
the desired operating frequency, should be connected as  
shown in Figure 10.  
The oscillator can be “trimmed” on–frequency by making a  
portion or all of C1 variable. The crystal and associated com-  
ponents must be located as close as possible to the OSC  
in  
and OSC  
out  
pins to minimize distortion, stray capacitance,  
stray inductance, and startup stabilization time. In some  
cases, stray capacitance should be added to the value for C  
in  
and C  
.
out  
Power is dissipated in the effective series resistance of the  
FREQUENCY  
R
f
SYNTHESIZER  
crystal, R , in Figure 12. The drive level specified by the crys-  
e
tal manufacturer is the maximum stress that a crystal can  
withstand without damage or excessive shift in frequency. R1  
in Figure 10 limits the drive level. The use of R1 may not be  
necessary in some cases (i.e., R1 = 0 ).  
To verify that the maximum dc supply voltage does not  
overdrive the crystal, monitor the output frequency as a func-  
OSC  
C1  
OSC  
out  
in  
R1*  
C2  
tion of voltage at OSC . (Care should be taken to minimize  
out  
loading.) The frequency should increase very slightly as the  
dc supply voltage is increased. An overdriven crystal will de-  
crease in frequency or become unstable with an increase in  
supply voltage. The operating supply voltage must be re-  
duced or R1 must be increased in value if the overdriven  
condition exists. The user should note that the oscillator  
start–up time is proportional to the value of R1.  
* May be deleted in certain cases. See text.  
Figure 10. Pierce Crystal Oscillator Circuit  
For V  
DD  
= 5.0 V, the crystal should be specified for a load-  
ing capacitance, C , which does not exceed 32 pF for fre-  
L
quencies to approximately 8.0 MHz, 20 pF for frequencies in  
the area of 8.0 to 15 MHz, and 10 pF for higher frequencies.  
These are guidelines that provide a reasonable compromise  
between IC capacitance, drive capability, swamping varia-  
tions in stray and IC input/output capacitance, and realistic  
Through the process of supplying crystals for use with  
CMOS inverters, many crystal manufacturers have devel-  
oped expertise in CMOS oscillator design with crystals. Dis-  
cussions with such manufacturers can prove very helpful  
(see Table 1).  
MOTOROLA  
MC145151–2 through MC145158–2  
29  
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