V62C21164096
UBE, LBE Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
Pin Descriptions
A –A Address Inputs
These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
0
17
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
CE , CE * Chip Enable Inputs
1
2
CE is active LOW and CE is active HIGH. Both
1
2
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
I/O –I/O
Data Input and Data Output Ports
1
16
These 16 bidirectional ports are used to read data
from and write data into the RAM.
OE
Output Enable Input
The output enable input is active LOW. With chip
enabled, when OE is Low and WE High, data will
be presented on the I/O pins. The I/O pins will be in
the high impedance state when OE is High.
V
Power Supply
Ground
CC
GND
*CE is available on BGA package only.
2
Pin Configurations (Top View)
44-Pin TSOP-II (Standard)
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UBE
LBE
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
CE1
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
A16
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
A9
A10
A11
A17
48 BGA
1
2
3
4
5
6
1
2
3
4
5
6
BLE OE A0 A1 A2 CE2
I/O9 BHE A3 A4 CE1 I/O1
I/O10 I/O11 A5 A6 I/O2 I/O3
VSS I/O12 A17 A7 I/O4 VCC
A
B
C
A
B
C
D
E
F
D
VCC I/O13 NC A16 I/O5 VSS
I/O15 I/O14 A14 A15 I/O6 I/O7
I/O16 NC A12 A13 WE I/O8
E
F
G
G
NC
A8 A9 A10 A11 NC
H
H
Note: NC means no connect.
TOP VIEW
TOP VIEW
V62C21164096 Rev. 1.6 October 2001
2
MOSEL [ MOSEL VITELIC, CORP ]
