MOSEL VITELIC
Signal Pin Description
Pin
CLK
CLK
CKE
V58C265804S
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS
WE
DQS
Input
Pulse
Input/
Output
Pulse
A0 - A11
Input
Level
BA0,
BA1
DQx
Input
Level
—
Selects which bank is to be active.
Input/
Output
Input
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high.
Power and ground for the input buffers and the core logic.
VDD, VSS Supply
VDDQ
VSSQ
VREF
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
SSTL Reference Voltage for Inputs
Input
Level
—
V58C265804S Rev. 1.3 January 2000
4
MOSEL [ MOSEL VITELIC, CORP ]
