MOSEL VITELIC
V58C265804S
HIGH PERFORMANCE
2.5 VOLT 8M X 8 DDR SDRAM
4 BANKS X 2Mbit X 8
PRELIMINARY
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK2
)
166 MHz
6 ns
6.5 ns
7ns
7
143 MHz
7 ns
7.5 ns
8ns
8
125 MHz
8 ns
9 ns
10ns
Features
s
4 banks x 2Mbit x 8 organization
s
High speed data transfer rates with system
frequency up to 166 MHz
s
Data Mask for Write Control (DM)
s
Four Banks controlled by BA0 & BA1
s
Programmable CAS Latency: 2, 2.5, 3
s
Programmable Wrap Sequence: Sequential
or Interleave
s
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
s
Automatic and Controlled Precharge Command
s
Suspend Mode and Power Down Mode
s
Auto Refresh and Self Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 66-pin 400 mil TSOP-II
s
SSTL-2 Compatible I/Os
s
Double Data Rate (DDR)
s
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
s
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
s
Differential clock inputs CLK and CLK
s
Power Supply 2.5V
±
0.2V
Description
The V58C265804S is a four bank DDR DRAM or-
ganized as 4 banks x 2Mbit x 8. The V58C265804S
achieves high speed data transfer rates by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
JEDEC 66 TSOP II
•
CLK Cycle Time (ns)
–6
•
Power
Std.
•
-7
•
-8
•
L
•
Temperature
Mark
Blank
V58C265804S Rev. 1.3 January 2000
1
MOSEL [ MOSEL VITELIC, CORP ]
