V58C2128(804/404/164)S
Figure 41 - SELF REFRESH MODE
t
CK
clock must be stable before
exiting Self Refresh mode
( (
) )
t
t
CH
CL
t
( (
) )
/CK
CK
( (
) )
( (
) )
t
t
t
t
IS
IS
IS IH
( (
) )
CKE
( (
) )
t
IS IH
( (
) )
( (
) )
COMMAND
NOP
AR
NOP
VALID
( (
) )
( (
) )
t
t
IS IH
( (
) )
( (
) )
ADDR
DQS
VALID
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQ
DM
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
XSNR/
tXSRD**
t
RP*
Enter
Self Refresh
Mode
Exit
Self Refresh
Mode
DON'T CARE
* = Device must be in the "All banks idle" state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CLK)
are required before a READ command can be applied.
V58C2128(804/404/164)S Rev. 1.6 March 2002
51