MOSEL VITELIC
V54C3128804VAT
V
54
C
31
V
A
T
28804
MOSEL-VITELIC
MANUFACTURED
SPEED
7 ns
PWR.
8 ns
SYCHRONOUS
DRAM FAMILY
C = CMOS PROCESS
DEVICE
NUMBER
PKG
BLANK (STANDARD)
T = TSOP-II
3.3V, LVTTL, INTERFACE
A = A VERSION
4 BANKS x 4Mbit x 8 (4K REFRESH)
Description Pkg.
TSOP-II
Pin Count
54
V = LVTTL
T
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
V
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
CC
I/O
CCQ
NC
2
3
4
I/O
V
NC
1
8
V
SSQ
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
I/O
SSQ
NC
5
6
7
I/O
V
NC
2
7
V
CCQ
I/O
CCQ
NC
8
9
I/O
V
NC
3
6
A –A
Address Inputs
Bank Select
0
11
V
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
BA0, BA1
I/O
I/O
V
4
5
I/O –I/O
Data Input/Output
Data Mask
V
SSQ
NC
CC
NC
WE
CAS
RAS
CS
CCQ
1
8
NC
DQM
V
V
SS
NC
V
V
V
V
Power (+3.3V)
Ground
CC
DQM
CLK
CKE
NC
SS
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
CCQ
SSQ
BA0
BA1
10
A
A
A
A
A
A
A
V
11
9
8
7
6
5
4
SS
A
NC
A
0
A
1
A
2
A
3
CC
V
V54C3128804VAT Rev. 1.4 November 2000
2
MOSEL [ MOSEL VITELIC, CORP ]
