MOSEL VITELIC
V54C3128804VAT
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 A11 A10 A9
Operation Mode
Address Bus (Ax)
A8 A7 A6 A5 A4 A3 A2 A1 A0
CAS Latency BT Burst Length
Mode Register
Burst Type
Operation Mode
A3
0
Type
BA1 BA0 A11 A10 A9 A8 A7
Mode
Sequential
Interleave
Burst Read/Burst
Write
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
Burst Read/Single
Write
Burst Length
CAS Latency
Length
A2
A1
A0
A6
0
A5
0
A4
Latency
Reserve
Reserve
2
Sequential Interleave
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
0
0
0
1
4
4
0
1
3
8
8
1
0
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
1
0
1
1
1
1
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
latches the sense amplifiers. The maximum t
or
sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.
RAS
the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
V54C3128804VAT Rev. 1.4 November 2000
7
MOSEL [ MOSEL VITELIC, CORP ]
