V437316S04V
SPD-Table
Hex Value
Byte Num-
ber
Function Described
SPD Entry Value
-75PC
-75
-10PC
28
Minimum Row Active to Row Active Delay
tRRD
15 ns
0E
0F
10
29
30
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
SDRAM Input Setup Time
20 ns
45 ns
0F
2A
20
15
08
15
08
00
14
2D
20
15
08
15
08
00
14
2D
20
20
10
20
10
00
31
128 MByte
1.5 ns
32
33
SDRAM Input Hold Time
0.8 ns
34
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
1.5 ns
35
0.8 ns
36-61
Superset Information (May be used in Fu-
ture)
62
63
SPD Revision
Revision 2
02
EC
40
00
02
31
40
00
02
8F
40
00
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
64
Mosel Vitelic
65-71
72
73-90
91-92
93
Module Part Number (ASCII)
PCB Identification Code
Assembly Manufacturing Date (Year)
Assembly Manufacturing Date (Week)
Assembly Serial Number
Reserved
V437316S04V
94
95-98
99-125
126
00
64
00
00
00
64
00
00
00
64
00
00
Intel Specification for Frequency
Reserved
127
128+
Unused Storage Location
DC Characteristics
T = 0°C to 70°C; V = 0 V; V , V = 3.3V ± 0.3V
DDQ
A
SS
DD
Limit Values
Symbol Parameter
Min.
Max.
Unit
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
–0.5
2.4
—
VCC+0.3
0.8
V
V
V
V
VOH
VOL
Output High Voltage (IOUT = –2.0 mA)
—
Output Low Voltage (IOUT = 2.0 mA)
0.4
V437316S04V Rev. 1.0 December 2001
5
MOSEL [ MOSEL VITELIC, CORP ]
