V436632Y24V
Serial Presence Detect Information
2
2
A serial presence detect storage device - E PROM -
is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
E PROM device during module production using a se-
2
rial presence detect protocol (I C synchronous 2-wire
bus)
SPD-Table for modules:
Hex Value
Byte
Number
Function Described
SPD Entry Value
-75PC
80
-75
80
08
04
0D
09
02
40
00
01
75
54
00
82
10
00
01
-10PC
80
0
1
Number of SPD bytes
128
Total bytes in Serial PD
256
08
08
2
Memory Type
SDRAM
04
04
3
Number of Row Addresses (without BS bits)
Number of Column Addresses ( x16 SDRAM)
Number of DIMM Banks
13
0D
09
0D
09
4
9
5
2
02
02
6
Module Data Width
64
0
40
40
7
Module Data Width (continued)
Module Interface Levels
00
00
8
LVTTL
01
01
9
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
7.5 ns/10.0 ns
5.4 ns/10.0ns
none
75
A0
60
10
11
12
13
14
15
54
00
00
Self-Refresh, 7.8 µs
x16
82
82
SDRAM width, Primary
10
10
Error Checking SDRAM Data Width
n/a / x16
00
00
Minimum Clock Delay from Back to Back Ran-
dom Column Address
tccd = 1 CLK
01
01
16
17
18
19
20
21
22
23
Burst Length Supported
1, 2, 4 & 8
4
0F
04
06
01
01
00
0E
75
0F
04
06
01
01
00
0E
A0
0F
04
06
01
01
00
0E
A0
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
CL = 2 / 3
CS Latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Non Buffered/Non Reg.
Vcc tol ± 10%
7.5 ns/10.0 ns &
Not Supported
24
Maximum Data Access Time from Clock for CL
= 2
7.5ns/10.0ns &
Not Supported
54
60
60
25
26
Minimum Clock Cycle Time at CL = 1
Not Supported
Not Supported
00
00
00
00
00
00
Maximum Data Access Time from Clock at CL
= 1
27
28
Minimum Row Precharge Time
15 ns / 20 ns
0F
0E
14
0F
14
10
Minimum Row Active to Row Active Delay tRRD
14 ns/15 ns/16 ns
V436632Y24V Rev. 1.2 March 2002
4
MOSEL [ MOSEL VITELIC, CORP ]
