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MSU2051C25 参数 Datasheet PDF下载

MSU2051C25图片预览
型号: MSU2051C25
PDF下载: 下载PDF文件 查看货源
内容描述: 低工作电压为16 MHz ROM MCU少 [low working voltage 16 MHz ROM less MCU]
分类和应用:
文件页数/大小: 21 页 / 121 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MO SEL VITELIC  
MSU2051/U2031  
#EA  
Pin Descriptions  
Vss  
When held at a TTL high level, the MSU2051 executes  
instructions from the internal ROM when the PC is less  
than 4096. When held at a TTL low level, the  
MSU2051 fetches all instuctions from external Program  
Memory.  
Circuit ground potential.  
VDD  
+3V (or +5 V) power supply during operation.  
XTAL 1  
PORT 0  
Input to the oscillator's high gain amplifier. A crystal or  
external source can be used.  
Port 0 is an 8-bit open drain bidirectional I/O port.  
It is also the multiplexed low-order address and data  
bus when using external memory.  
XTAL 2  
Output from the oscillator's amplifier. Required when a  
crystal is used.  
PORT 1  
Port 1 is an 8-bit quasi-bidirectional I/O port with  
internal pull-up resistance.  
Terms  
PORT 2  
Idle Mode  
Port 2 is an 8-bit quasi-bidirectional I/O port with  
internal pull-up resistance. It also emit the high-order  
address byte when accessing external memory.  
During idle mode, the CPU is stopped but below blocks  
are kept functioning: clock generator, RAM, timer/  
counters, serial port and interrupt block. To save power  
consumption, user's software program can invoke this  
mode. The on-chip data RAM retains the values during  
this mode, but the processor stops executing  
instructions. In Idle mode (IDL=1), the oscillator  
continues to run and the interrput, and timer blocks  
continue to be clocked but the clock signal is gated off  
to the CPU. The activities of the CPU no longer exist  
unless waiting for an interrupt request.  
-An instruction that sets flag (PCON.0) causes that to be  
the last instruction executed before going into the Idle  
Mode.  
-In the Idle Mode, the internal clock signal is gated off to  
the CPU, but not to the interrupt, Timer function.  
-The CPU status is entirely preserved in its:  
the Stack Pointer, Program Counter, Program Status  
Word, Accumulator, and all other registers maintain  
their data during Idle mode.  
PORT 3  
Port 3 is an 8-bit quasi-bidirectinal I/O port with internal  
pull-up resistance. It also contains the interrupt, timer,  
serial port and #RD as well as #WR pins that are used  
by various options. The output latch corresponding to a  
secondary function must be programmed to one (1) for  
that function to operate. The secondary functions are  
assigned to the pins of port 3, as follows:  
- RXD/data (P3.0). Serial port's transmitter data output  
(asynchronous) or data input/output (asynchronous).  
- TXD/clock (P3.1). Serial port's transmitter data  
output (asynchronous) or data output (asynchronous).  
- #INT0 (P3.2). Interrupt 0 input or gate control input  
for counter 0.  
- #INT1 (P3.3). Interrupt 1 input or gate control input  
for counter 1.  
- T0 (P3.4). Input to counter 0.  
- T1 (P3.4). Input to counter 1.  
-There are three ways to terminate the Idle Mode.  
1) By interrupt  
Activation of any enabled interrupt will cause flag  
(PCON.0) to be cleared by hardware, termination the  
Idle Mode. After the program wakes up, the PC value  
will point as interrupt vector (if enable IE register) and  
execute interrupt service routine then return to PC+1  
address after the program wakes up.  
- #WR (P3.6). The write control signal latches the data  
byte from Port 0 into the External Data Memory.  
- #RD (P3.7). The read control signal enables External  
Data Memory to Port 0.  
RES  
2) By hardware reset  
Since the clock oscillator is still running, the hardware  
reset needs to be held active for only two machine  
cycles (24 oscillator periods) to complete the reset. All  
SFR and PC value will be cleared to reset value.  
3) By one of CLK, DATA, PORT 2.0-2.7 transition to  
low (falling edge trigger)  
After the program wakes up, the PC value will be  
0023h (if enable IE register) and execute interrupt  
service routine and then returns to PC+1 address after  
the program wakes up.  
A high on this pin for two machine cycles (24 clocks)  
while the oscillator is running, resets the device. The  
data in RAM is preserved when reset signals - reset  
does not clear the data in RAM.  
ALE  
Provides Address Latch Enable output used for latching  
the address into external memory during normal opera-  
tion.  
#PSEN  
The Program Store Enable output is a control signal that  
enables the external Program Memory to the bus during  
normal fetch operations.  
Rev. 1.0 February 1998  
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