PUMA2/67/77S4000/A-020/025/35
Issue4.3:December1999
Operating Modes
The table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
modules.
Mode
CS OE WE
VCC Current
I/O Pin Reference Cycle
Not Selected
Output Disable
Read
1
0
0
0
X
1
X
1
1
0
ISB1,ISB2
ICC
High Z
High Z
DOUT
Power Down
-
0
ICC
Read Cycle
Write Cycle
Write
X
ICC
DIN
1 = VIH,
0 = VIL,
X = Don't Care
Note: CS above is accessed through CS1~4 (and WE by WE1~4 on the PUMA 2S4000, 67S4000A, 77S4000A). For correct
operation, CS1~ 4 (and WE1~4) must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or
singly for 8 bit operation.
AC Test Conditions
*Input pulse levels: 0.0V to 3.0V
Output Load
I/O Pin
166Ω
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*Vcc=5V±10%
1.76V
30pF
*PUMA module is tested in 32 bit mode.
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
Symbol Test Condition
VDR
min
typ
-
max Unit
VCC for Data Retention
Data Retention Current
CS1~4 ≥ VCC-0.2V
2
-
V
ICCDR VCC = 3.0V, CS1~4 ≥ VCC-0.2V,
VIN ≥ VCC-0.2V or ≤ 0.2V
-
-
-
-
-
-
20
-
mA
ns
Chip Deselect to Data Retention tCDR
Operation Recovery Time tR
See Retention Waveform
See Retention Waveform
-
ns
3
MOSAIC [ MOSAIC ]
