MSM8129JXL-12 参数 Datasheet PDF下载

MSM8129 - 70/85/10/12

Issue 1.0 : February 2000

Operating Modes

The table below shows the logic inputs required to control the MSM8128 SRAM.

Mode

Not Selected

Not Selected

Output Disable

Read

Write

CS1

1

X

0

0

0

CS2

X

0

1

1

1

OE

X

X

1

0

X

WE

X

X

1

1

0

V

CC

Current

I

SB1

,I

SB2

I

SB

,I

SB1

I

CC

I

CC

I

CC

X = Don't Care

I/O Pin

High Z

High Z

High Z

D

OUT

D

IN

Reference Cycle

Power Down

Power Down

Read Cycle

Write Cycle

1 = V

IH

,

0 = V

IL

,

Low V

cc

Data Retention Characteristics - L Version Only

(T

A

=-55°C to +125

o

C)

Parameter

V

CC

for Data Retention

Data Retention Current

Chip Deselect to Data Retention

Operation Recovery Time

Symbol Test Condition

V

DR

I

CCDR

t

CDR

t

R

CS1

≥

V

CC

-0.2V, CS2

≥

V

CC

-0.2V or

0V

≤

CS2

≤

0.2V. V

IN

≥

0V

V

CC

=3.0V,V

IN

≥

0V, CS1

≥

V

CC

-0.2V,

CS2

≥

V

CC

-0.2V or 0V

≤

CS2

≤

0.2V.

See Retention Waveform

See Retention Waveform

min

2.0

-

0

5

typ

-

-

-

-

max

-

600

-

-

Unit

V

µA

ns

ms

Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,

Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,

CS2 must be

≥

V

CC

- 0.2V or 0V

≤

CS2

≤

0.2V. The other input levels (address, WE,OE,I/O) can be in the

high impedance state.

AC Test Conditions

* Input pulse levels: 0V to 3.0V

* Input rise and fall times: 5ns

* Input and Output timing reference levels: 1.5V

* Output load: See Load Diagram

* V

cc

=5V±10%

Output Load

I/O Pin

166

Ω

1.76V

30pF

3