128K x 8 SRAM
MSM8129 - 70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230
Issue 1.0 : February 2000
Description
The MSM8129 is a 1Mbit monolithic SRAM
organised as 128K x 8. It is currently available in
JLCC package, with access times of 70, 85,
100, 120ns. It has a low power standby version
and has 3.0V battery backup capability. It is
directly TTL compatible and has common data
inputs and outputs.
Two pinout variants (single and dual CS) are
available.
All versions may be screened in accordance with
MIL-STD-883.
131,072 x 8 CMOS Static RAM
Features
Access Times of 70/85/100/120 ns
Standard Dual CS footprint.
Operating Power
550 mW (max)
Low Power Standby (-L) 2.2 mW (max)
Low Voltage Data Retention.
Completely Static Operation
Directly TTL compatible.
May be processed in accordance with MIL-STD-883
Block Diagram
Pin Definition
D0
A0
A1
A2
A3
A4
A5
A6
A7
13
12
11
10
9
8
7
6
5
MEMORY ARRAY
512 X 2048
D1
D2
GND
D3
D4
D5
D6
14
15
16
17
18
19
20
TOP VIEW
J
21
22
23
24
25
26
27
28
29
4
3
2
1
32
31
30
A12
A14
A16
NC
VCC
A15
CS2
13
12
11
10
9
8
7
6
5
D0
A0
A1
A2
A3
A4
A5
A6
A7
D7
CS1
A10
OE
A11
A9
A8
A13
WE
D1
D2
GND
D3
D4
D5
D6
14
15
16
17
18
19
20
TOP VIEW
JX
21
22
23
24
25
26
27
28
29
4
3
2
1
32
31
30
A12
A14
A16
NC
VCC
A15
NC
Package Details
Pin Count
Description
32
J-Leaded Chip Carrier (JLCC)
Package Type
J
Package details on pages 9.
Pin Functions
A0~A16
Address Inputs
D0-7
Data Input/Output
CS1
Chip Select 1
CS2
Chip Select 2
OE
Output Enable
WE
Write Enable
NC
No Connect
V
CC
Power (+5V)
GND
Ground
CS
A10
OE
A11
A9
A8
A13
WE
D7
MOSAIC [ MOSAIC ]
