MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
nal, and one software.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software
interrupt set by the BRK instruction. An interrupt occurs if the cor-
responding interrupt request and enable bits are “1” and the
interrupt disable flag is “0”.
ꢀNotes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit or the interrupt source select bit
to “1”.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
ꢀSet the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
ꢀSet the corresponding interrupt enable bit to “1” (enabled).
Table 10 Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
At reset
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
At detection of either rising or External interrupt
falling edge of INT0 input
(active edge selectable)
INT1
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
At detection of either rising or External interrupt
3
4
5
falling edge of INT1 input
(active edge selectable)
Serial I/O
reception
At completion of serial I/O data
reception
Valid when serial I/O is selected
At completion of serial I/O trans-
mit shift or when transmission
buffer is empty
Serial I/O
transmission
Valid when serial I/O is selected
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
8
9
At detection of either rising or
falling edge of CNTR0 input
10
External interrupt
(active edge selectable)
CNTR1
11
FFE916
FFE816
At detection of either rising or External interrupt
falling edge of CNTR1 input
(active edge selectable)
Timer 1
INT2
12
13
FFE716
FFE516
FFE616
FFE416
At timer 1 underflow
At detection of either rising or External interrupt
falling edge of INT2 input
(active edge selectable)
INT3
At detection of either rising or
falling edge of INT3 input
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
External interrupt
(active edge selectable)
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode)
(Valid at falling)
ADT
At falling of ADT input
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
At completion of A-D conversion
At BRK instruction execution
A-D conversion
BRK instruction
Valid when A-D interrupt is se-
lected
17
FFDD16
FFDC16
Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
22
MITSUBISHI [ Mitsubishi Group ]
