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M37270EFSP 参数 Datasheet PDF下载

M37270EFSP图片预览
型号: M37270EFSP
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位CMOS单片机结合闭合字幕解码器和屏幕显示控制器 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER]
分类和应用: 解码器显示控制器瞄准线计算机
文件页数/大小: 94 页 / 1543 K
品牌: MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
SERIAL I/O
The M37270MF-XXXSP has a built-in serial I/O which can either trans-
mit or receive 8-bit data in serial in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 9. The synchronizing
clock I/O pin (S
CLK
), and data output pin (S
OUT
) also function as port
P4, data input pin (S
IN
) also functions as port P1.
Bit 2 of the serial I/O mode register (address 0213
16
) selects whether
the synchronizing clock is supplied internally or externally (from the
P4
6
/S
CLK
pin). When an internal clock is selected, bits 1 and 0 select
whether f(X
IN
) or f(X
CIN
) is divided by 8, 16, 32, or 64. To use P4
5
/
S
OUT
and P4
6
/S
CLK
pins for serial I/O, set the corresponding bits of
the port P4 direction register (address 00C9
16
) to “0.” To use P1
7
/S
IN
pin for serial I/O, set the corresponding bit of the port P1 direction
register (address 00C3
16
) to “0.”
The operation of the serial I/O function is described below. The func-
tion of the serial I/O differs depending on the clock source; external
clock or internal clock.
X
CIN
1/2
X
IN
1/2
CM
7
Synchronization
circuit
Data bus
1/2
Frequency divider
1/2
1/4
1/8
1/16
SM
2
S
SM
1
SM
0
Selection gate: Connect to
black colored
side at reset.
P4
6
/S
CLK
Serial I/O counter (8)
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O
interrupt request
P4
5
/S
OUT
P1
7
/S
IN
SM
5
: LSB
MSB
(Note)
Serial I/O shift register (8)
8 (Address 0214
16
)
Note :
When the data is set in the serial I/O register (address 0214
16
), the register functions as the serial I/O shift register.
Fig. 9. Serial I/O block diagram
17