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M34280M1 参数 Datasheet PDF下载

M34280M1图片预览
型号: M34280M1
PDF下载: 下载PDF文件 查看货源
内容描述: 单片4位微机的CMOS红外遥控变送器 [SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS]
分类和应用: 遥控远程控制计算机
文件页数/大小: 47 页 / 505 K
品牌: MITSUBISHI [ Mitsubishi Group ]
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MITSUBISHI MICROCOMPUTERS  
4280 Group  
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS  
FUNCTION BLOCK OPERATIONS  
CPU  
<Carry>  
(CY)  
(1) Arithmetic logic unit (ALU)  
The arithmetic logic unit ALU performs 4-bit arithmetic such  
as 4-bit data addition, comparison, and bit manipulation.  
(M(DP))  
Addition  
ALU  
(2) Register A and carry flag  
(A)  
Register A is a 4-bit register used for arithmetic, transfer,  
exchange, and I/O operation.  
<Result>  
Carry flag CY is a 1-bit flag that is set to “1” when there is a  
carry with the AMC instruction (Figure 1).  
Fig. 1 AMC instruction execution example  
It is unchanged with both A n instruction and AM instruction.  
The value of A0 is stored in carry flag CY with the RAR  
instruction (Figure 2).  
<Set>  
SC instruction  
<Clear>  
RC instruction  
Carry flag CY can be set to “1” with the SC instruction and  
cleared to “0” with the RC instruction.  
CY  
A3 A2 A1 A0  
(3) Registers B and E  
Register B is a 4-bit register used for temporary storage of 4-  
bit data, and for 8-bit data transfer together with register A.  
Register E is an 8-bit register. It can be used for 8-bit data  
transfer with register B used as the high-order 4 bits and  
register A as the low-order 4 bits (Figure 3).  
<Rotation>  
RAR instruction  
A0  
CY A3 A2 A1  
Fig. 2 RAR instruction execution example  
(4) Register D  
Register D is a 3-bit register.  
TAB instruction  
Register B  
It is used to store a 7-bit ROM address together with register  
A and is used as a pointer within the specified page when the  
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).  
Register A  
B3  
B2  
B1  
B0  
A3 A2 A1 A0  
TEAB instruction  
Register E ER  
7
ER6  
ER5ER4ER3ER2ER1ER0  
TABE instruction  
B3 B2 B1 B0  
A3 A2 A1 A0  
Register B TBA instruction Register A  
Fig. 3 Registers A, B and register E  
ROM  
4
TABP p instruction  
Specifying address  
8
0
Low-order 4 bits  
Register A (4)  
PCH  
p3 p2 p1 p0  
PCL  
A3 A2 A1 A0  
DR2 DR1DR0  
Middle-order 4 bits  
Register B (4)  
Most significant 1 bit  
The contents The contents  
of register D of register A  
Immediate field  
value p  
Carry flag CY (1)  
URS flag (1)  
URSC instruction  
Fig. 4 TABP p instruction execution example  
MITSUBISHI  
ELECTRIC  
6
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