Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt control register
Symbol
BCNIC
DMiIC(i=0, 1)
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Address
When reset
004A16
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
b7 b6 b5 b4 b3 b2 b1 b0
R
W
Bit symbol
Bit name
Function
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Symbol
Address
When reset
XX00X000
b7 b6 b5 b4 b3 b2 b1 b0
INTiIC(i=0 to 2) 005D16 to 005F16
2
0
R
W
Bit symbol
Bit name
Function
Interrupt priority level
select bit
ILVL0
ILVL1
ILVL2
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
Polarity select bit
IR
0: Interrupt not requested
1: Interrupt requested
(Note 1)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Always set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.13.3. Interrupt control registers
46