PDSP16488A MA
IP7:0
1024
3 X 3 WINDOW
LINE N-1
LINE N
C4
C8
C0
C5
C9
C1
C6
C10
C2
FIELD
DELAY
N+1
N-1
ODD
FIELD
1024
4X4
OR
8X4
ARRAY
VIDEO
LINE N+2
L7:0
1024
N
LINE N+1
1024
Output is shifted
by 1 line in
every field
5 X 5 WINDOW
LINE N-2
C48
C49
C50
C51
C52
IP7:0
512
ODD
FIELD
512
FIELD
DELAY
512
512
N+1
N-1
LINE N-1
LINE N
C8
C40
C9
C41
C10
C42
C11
C43
C12
C44
LINE N+1
C0
C32
C1
C33
C2
C34
C3
C35
C4
C36
LINE N+2
VIDEO
LINE N+2
L7:0
512
512
*
N+2
N
N-2
8X8
ARRAY
Output is shifted
by 1 line in
every field
*
Delay is By-Passed
[REG B,BIT 7 IS SET]
512
512
8 X 8 WINDOW
LINE N-3
C24
C25
C26
C27
C28
C29
C30
C31
ODD
FIELD
IP7:0
512
512
FIELD
DELAY
C23
512
512
C55
N+3
N+1
N-1
N-3
LINE N-2
LINE N-1
C56
C57
C58
C59
C60
C61
C62
C63
C16
C17
C18
C19
C20
C21
C22
LINE N
C48
C49
C50
C51
C52
C53
C54
L7:0
LINE N+1
C8
C9
C10
C11
C12
C13
C14
C15
VIDEO
LINE N+4
512
512
*
N+4
N+2
N
N-2
8X8
ARRAY
Output is shifted
by 2 lines in
every field
LINE N+2
C40
C41
C42
C43
C44
C45
C46
C47
LINE N+3
C0
C1
C2
C3
C4
C5
C6
C7
*
Delay is By-Passed
[REG B,BIT 7 IS SET]
512
512
LINE N+4
C32
C33
C34
C35
C36
C37
C38
C39
Figure 3. Line Delay Allocations in Single Device Interlaced Systems
5
MITEL [ MITEL NETWORKS CORPORATION ]
