PDSP16488A MA
IP7:0
1024
1024
N+1
FIELD
DELAY
ODD
FIELD
3 X 3 WINDOW
C4
C5
C6
LINE N-1
LINE N
N - 1
L7:0
4 X 4
OR
VIDEO
Output is shifted
by 1 line in
C8
C0
C9
C1
C10
C2
8 X 4
LINE N+2
1024
1024
ARRAY
N
every field
LINE N+1
5 X 5 WINDOW
IP7:0
LINE N-2
512
512
512
512
C48
C49
C50
C51
C52
N+1
N-1
ODD
FIELD
LINE N-1
LINE N
C8
C9
C10
C42
C11
C43
C12
C44
FIELD
DELAY
C40
C41
LINE N+1
LINE N+2
C0
C1
C2
C3
C4
L7:0
VIDEO
LINE N+2
Output is shifted
by 1 line in
8 X 8
ARRAY
*
C32
C33
C34
C35 C36
512
512
512
512
N+2
every field
N
*
Delay is By-Passed
N-2
[REG B,BIT 7 IS SET]
8 X 8 WINDOW
IP7:0
C24
C25
C26
C27
C28
C29
C61
C30
C62
C31
C63
LINE N-3
512
512
512
512
N+3
ODD
FIELD
C56
C57
C58
C59
C60
LINE N-2
LINE N-1
N+1
N-1
FIELD
DELAY
C16 C17
C18
C19
C51
C20
C52
C21
C53
C22
C54
C23
C55
N-3
C48
C8
C49
C50
C10
LINE N
L7:0
Output is shifted
by 2 lines in
every field
8 X 8
ARRAY
*
LINE N+1
VIDEO
512
512
512
512
C9
C11
C43
C3
C12
C44
C4
C13
C45
C5
C14
C46
C6
C15
C47
C7
N+4
LINE N+4
LINE N+2
LINE N+3
C40 C41
C42
N+2
N
*
Delay is By-Passed
[REG B,BIT 7 IS SET]
C0
C1
C2
N-2
C32
C33
C34
C35
C36 C37
C38
LINE N+4
C39
Figure 3. Line Delay Allocations in Single Device Interlaced Systems
5
MITEL [ MITEL NETWORKS CORPORATION ]
