PDSP16488A MA
MULTI PURPOSE
DATA BUS
X15:0
CE DS R/W PC0 PC1 RSE CS3:0
PROG
MASTER
CONTROL
X
SINGLE
DELOP
CONTROL
REGISTERS
DELAY
Y
IP7:0
COEFFICIENT
STORE (64)
DELAY
BIN
COMPARATOR
1
BY
PASS
LINE
DELAY
3
LINE
DLYS
OVER
FLOW
8 X 8
ARRAY OF
MAC'S
Y
L7:0
DELAY
4
LINE
DLYS
D15:0
DATA
OUT
OEN
CLOCK
Fig. 2 Functional Block Diagram
PIN NO
AC PACKAGE
PIN NO
AC PACKAGE
PIN NO
FUNCTION
PIN NO
AC PACKAGE
FUNCTION
FUNCTION
FUNCTION
AC PACKAGE
RES
CS0
CS1
CS2
CS3
PROG
DS
X15
X14
X13
SPARE
SINGLE
X12
X11
MASTER
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
K12
K13
J12
M3
N3
M4
N4
M5
N5
M6
M7
N7
M8
N9
M9
N10
M10
N11
M11
N12
N13
M13
L12
L13
B9
A9
B8
B7
A7
B6
A5
B5
A4
B4
A3
B3
A2
F1
N6
F13
A6
H1
N8
H13
A8
D7
D8
CLK
SPARE
D9
L0
F1
L1
L2
L3
SPARE
L4
L5
L6
L7
IP7
SPARE
IP6
IP5
IP4
SPARE
IP3
IP2
IP1
A1
B1
C2
C1
D2
D1
E2
E1
F2
G2
G1
H2
J1
J13
H12
G12
G13
F12
E13
E12
D13
D12
C13
C12
B13
A13
A12
B11
A11
B10
A10
D10
D11
SPARE
D12
D13
D14
D15
F0
VDD
VDD
VDD
VDD
GND
GND
GND
GND
CE
R/W
HRES
OV
PC1
BIN
OEN
D0
D1
D2
D3
D4
J2
K1
K2
L1
L2
X0
DELOP
PC0
M1
N1
N2
D5
D6
IP0
BYPASS
Pin out Table (84 pin PGA - AC84)
2
MITEL [ MITEL NETWORKS CORPORATION ]
