MT91L60/61
address information, the Command/Address byte is
defined differently for Intel operation than it is for
Motorola/National operation. Refer to the relative
timing diagrams of Figures 5 and 6.
Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.
Flexible Digital Interface
A serial link is required to transport data between the
MT91L60/61 and an external digital transmission
device. The MT91L60/61 utilizes the ST-BUS
architecture defined by Mitel Semiconductor but also
supports a strobed data interface found on many
standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI). The
combination of ST-BUS and SSI provides a Flexible
Digital Interface (FDI) capable of supporting all Mitel
basic rate transmission devices as well as many
other 2B+D transceivers.
The required mode of operation is selected via the
CSL2-0 control bits (Control Register 2, address
04h). Pin definitions alter dependent upon the
operational mode selected, as described in the
following subsections as well as in the Pin
Description tables.
Quiet Code
The FDI can be made to send quiet code to the
decoder and receive filter path by setting the RxMute
bit high. Likewise, the FDI will send quiet code in the
transmit path when the TxMute bit is high. Both of
these control bits reside in Control Register 1 at
address 03h. When either of these bits are low their
respective paths function normally. The -Zero entry
of Table 1 is used for the quiet code definition.
ST-BUS Mode
The ST-BUS consists of output (DSTo) and input
(DSTi) serial data streams, in FDI these are named
Dout and Din respectively, a synchronous clock input
signal CLOCKin (C4i), and a framing pulse input
(F0i). These signals are direct connections to the
corresponding pins of Mitel basic rate devices. The
CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS
operation.
The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to separate the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125
µSecond
period translating into an 8
kHz frame rate. A valid frame begins when F0i is
6
Preliminary Information
logic low coincident with a falling edge of C4i. Refer
to Figure 11 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used to
clock the MT91L60/61 internal functions (i.e., Filter/
Codec, Digital gain and tone generation) and to
provide the channel timing requirements.
The MT91L60/61 uses only the first four channels of
the 32 channel frame. These channels are always
defined, beginning with Channel 0 after the frame
pulse, as shown in Figure 6 (ST-BUS channel
assignments). The MT91L60/61 provides a delayed
frame pulse (F0od), 4 channels after the input frame
pulse.
The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (Control
Register 2, address 04h). ISDN basic rate service
(2B+D) defines a 16 kb/s signalling (D) Channel. The
MT91L60/61 supports transparent access to this
signalling channel. ST-BUS basic rate transmission
devices, which may not employ a microport, provide
access to their internal control/status registers
through the ST-BUS Control (C) Channel. The
MT91L60/61 supports microport access to this
C-Channel.
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 06h). D-Channel data is
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.
DEN:
When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).
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